MC74HC1G00DFT2

MC74HC1G00 Single 2−Input NAND Gate The MC74HC1G00 is a high speed CMOS 2−input NAND gate fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output. • • • • • • • High Speed: tPD = 7 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1
A (Max) at TA = 25°C http://onsemi.com High Noise Immunity Balanced Propagation Delays (tPLH = tPHL) MARKING DIAGRAMS Symmetrical Output Impedance (IOH = IOL = 2 mA) Chip Complexity: FETs = 40 Pb−Free Packages are Available 5 H1d 1 SC70−5/SC−88A/SOT−353 DF SUFFIX CASE 419A IN B 1 IN A 2 5 Pin 1 VCC 5 H1M 1 3 GND 4 SOT23−5/TSOP−5/SC59−5 DT SUFFIX CASE 483 OUT Y Figure 1. Pinout (Top View) IN A & Pin 1 d = Date Code M = Month Code PIN ASSIGNMENT OUT Y IN B Figure 2. Logic Symbol 1 IN B 2 IN A 3 GND 4 OUT Y 5 VCC FUNCTION TABLE Output Inputs A B Y L L H H L H L H H H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.  Semiconductor Components Industries, LLC, 2005 January, 2005 − Rev. 9 1 Publication Order Number: MC74HC1G00/D MC74HC1G00 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage 0.5 to 7.0 V VIN DC Input Voltage 0.5 to VCC 0.5 V VOUT DC Output Voltage 0.5 to VCC 0.5 V IIK DC Input Diode Current
20 mA IOK DC Output Diode Current
20 mA IOUT DC Output Sink Current
12.5 mA ICC DC Supply Current per Supply Pin
25 mA TSTG Storage Temperature Range 65 to 150
C TL Lead Temperature, 1 mm from Case for 10 Seconds 260
C TJ Junction Temperature Under Bias JA Thermal Resistance PD Power Dissipation in Still Air at 85
C MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage ILATCHUP Latchup Performance 150
C SC70−5/SC−88A (Note 1) TSOP−5 350 230
C/W SC70−5/SC−88A TSOP−5 150 200 mW Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) 2000 200 N/A V Above VCC and Below GND at 125
C (Note 5)
500 mA Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Min Max Unit VCC DC Supply Voltage Parameter 2.0 6.0 V VIN DC Input Voltage 0.0 VCC V VOUT DC Output Voltage 0.0 VCC V TA Operating Temperature Range 55 125
C tr , tf Input Rise and Fall Time 0 0 0 0 1000 600 500 400 ns VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80
C 1,032,200 TJ = 90
C 80 TJ = 100
C Time, Years TJ = 110
C Time, Hours FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 120
C Junction Temperature °C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES TJ = 130
C Symbol 1 1 10 100 1000 TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 MC74HC1G00 DC ELECTRICAL CHARACTERISTICS VCC Symbol Parameter Test Conditions (V) Min 1.5 2.1 3.15 4.20 VIH Minimum High−Level Input Voltage 2.0 3.0 4.5 6.0 VIL Maximum Low−Level Input Voltage 2.0 3.0 4.5 6.0 VOH Minimum High−Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = −20
A VIN = VIH or VIL IOH = −2 mA IOH = −2.6 mA VOL Maximum Low−Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 20
A TA  85
C TA = 25
C Typ Max Min
55
C  TA  125
C Max Min 1.5 2.1 3.15 4.20 0.5 0.9 1.35 1.80 Max 1.5 2.1 3.15 4.20 0.5 0.9 1.35 1.80 V 0.5 0.9 1.35 1.80 2.0 3.0 4.5 6.0 1.9 2.9 4.4 5.9 2.0 3.0 4.5 6.0 1.9 2.9 4.4 5.9 1.9 2.9 4.4 5.9 4.5 6.0 4.18 5.68 4.31 5.80 4.13 5.63 4.08 5.58 Unit V V 2.0 3.0 4.5 6.0 0.0 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN = VIH or VIL IOL = 2 mA IOL = 2.6 mA 4.5 6.0 0.17 0.18 0.26 0.26 0.33 0.33 0.40 0.40 V IIN Maximum Input Leakage Current VIN = 6.0 V or GND 6.0
0.1
1.0
1.0
A ICC Maximum Quiescent Supply Current VIN = VCC or GND 6.0 1.0 10 40
A AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 6.0 ns) TA  85
C TA = 25
C
55
C  TA  125
C ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ Symbol Parameter tPLH, tPHL Maximum Propagation Delay Delay, Input A or B to Y tTLH, tTHL Output Transition Time CIN Maximum Input Capacitance Test Conditions Min Typ Max Min Max Min Max Unit ns VCC = 5.0 V CL = 15 pF 3.5 15 20 25 VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V CL = 50 pF 19 10.5 7.5 6.5 100 27 20 17 125 35 25 21 155 90 35 26 VCC = 5.0 V CL = 15 pF 3 10 15 20 VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V CL = 50 pF 25 16 11 9 125 35 25 21 155 45 31 26 200 60 38 32 5 10 10 10 ns pF Typical @ 25
C, VCC = 5.0 V CPD Power Dissipation Capacitance (Note 6) 10 pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD
VCC
fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD
VCC2
fin + ICC
VCC. http://onsemi.com 3 MC74HC1G00 VCC INPUT A or B 90% 50% 10% tf tr VCC CL* GND tPLH OUTPUT Y OUTPUT INPUT tPHL 90% 50% 10% tTLH *Includes all probe and jig capacitance. A 1−MHz square input wave is recommended for propagation delay tests. tTHL Figure 4. Switching Waveforms Figure 5. Test Circuit DEVICE ORDERING INFORMATION Device Nomenclature Logic Circuit Indicator Temp Range Identifier Technology Device Function Package Suffix Tape and Reel Suffix MC74HC1G00DFT1 MC 74 HC1G 00 DF MC74HC1G00DFT1G MC 74 HC1G 00 MC74HC1G00DFT2 MC 74 HC1G MC74HC1G00DFT2G MC 74 MC74HC1G00DTT1 MC MC74HC1G00DTT1G MC Device Order Number Package Type Tape and Reel Size† T1 SC70−5/SC−88A/ SOT−353 178 mm (7 in) 3000 Unit DF T1 SC70−5/SC−88A/ SOT−353 (Pb−Free) 178 mm (7 in) 3000 Unit 00 DF T2 SC70−5/SC−88A/ SOT−353 178 mm (7 in) 3000 Unit HC1G 00 DF T2 SC70−5/SC−88A/ SOT−353 (Pb−Free) 178 mm (7 in) 3000 Unit 74 HC1G 00 DT T1 SOT23−5/TSOP−5/ SC59−5 178 mm (7 in) 3000 Unit 74 HC1G 00 DT T1 SOT23−5/TSOP−5/ SC59−5 (Pb−Free) 178 mm (7 in) 3000 Unit †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74HC1G00 PACKAGE DIMENSIONS SC70−5/SC−88A/SOT−353 DF SUFFIX 5−LEAD PACKAGE CASE 419A−02 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. A G 5 4 DIM A B C D G H J K N S −B− S 1 2 3 D 5 PL 0.2 (0.008) M B M N INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC −−− 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 J C K H SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm  inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC −−− 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 MC74HC1G00 SOT23−5/TSOP−5/SC59−5 DT SUFFIX 5−LEAD PACKAGE CASE 483−02 ISSUE C D S 5 4 1 2 3 B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. A AND B DIMENSIONS DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. L G DIM A B C D G H J K L M S A J C 0.05 (0.002) H M K MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm  inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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