MC74HC245A
Octal 3−State Noninverting
Bus Transceiver
High−Performance Silicon−Gate CMOS
The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The HC245A is a 3−state noninverting transceiver that is used for
2−way asynchronous communication between data buses. The device
has an active−low Output Enable pin, which is used to place the I/O
ports into high−impedance states. The Direction control determines
whether data flows from A to B or from B to A.
Features
•
•
•
•
•
•
•
•
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MARKING
DIAGRAMS
20
20
PDIP−20
N SUFFIX
CASE 738
MC74HC245AN
AWLYYWWG
1
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 308 FETs or 77 Equivalent Gates
Pb−Free Packages are Available*
1
20
20
1
SOIC−20
DW SUFFIX
CASE 751D
HC245A
AWLYYWWG
1
20
20
1
HC
245A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
1
20
1
20
SOEIAJ−20
F SUFFIX
CASE 967
1
74HC245A
AWLYWWG
A
=
Assembly Location
WL, L
=
Wafer Lot
YY, Y
=
Year
WW, W =
Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 12
1
Publication Order Number:
MC74HC245A/D
MC74HC245A
DIRECTION
A1
A2
20
1
VCC
OUTPUT ENABLE
19
2
18
3
A1
A2
A3
B1
A3
4
17
B2
A4
5
16
B3
A5
6
15
B4
A6
7
14
B5
A7
8
13
B6
A8
9
12
B7
10
11
B8
A
DATA
PORT
A4
A5
A6
GND
A7
A8
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
B1
B2
B3
B4
B5
B
DATA
PORT
B6
B7
B8
1
DIRECTION
19
OUTPUT ENABLE
PIN 10 = GND
PIN 20 = VCC
Figure 1. Pin Assignment
Figure 2. Logic Diagram
FUNCTION TABLE
Control Inputs
Output
Enable
Direction
L
L
Data Transmitted from Bus B to Bus A
L
H
Data Transmitted from Bus A to Bus B
H
X
Buses Isolated (High−Impedance State)
Operation
X = don’t care
ORDERING INFORMATION
Package
Shipping †
MC74HC245AN
PDIP−20
18 Units / Rail
MC74HC245ANG
PDIP−20
(Pb−Free)
18 Units / Rail
MC74HC245ADW
SOIC−20 WIDE
38 Units / Rail
MC74HC245ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HC245ADWR2
SOIC−20 WIDE
1000 Tape & Reel
MC74HC245ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
MC74HC245ADT
TSSOP−20*
75 Units / Rail
MC74HC245ADTG
TSSOP−20*
75 Units / Rail
MC74HC245ADTR2
TSSOP−20*
2500 Tape & Reel
MC74HC245ADTR2G
TSSOP−20*
2500 Tape & Reel
MC74HC245AF
SOEIAJ−20
40 Units / Rail
MC74HC245AFG
SOEIAJ−20
(Pb−Free)
40 Units / Rail
MC74HC245AFEL
SOEIAJ−20
2000 Tape & Reel
MC74HC245AFELG
SOEIAJ−20
(Pb−Free)
2000 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HC245A
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Output Voltage
(Note 2)
Value
Unit
*0.5 to )7.0
V
*0.5 to VCC )0.5
V
*0.5 to VCC )0.5
V
IIK
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$35
mA
IOUT
DC Output Sink Current
$35
mA
ICC
DC Supply Current per Supply Pin
$75
mA
IGND
DC Ground Current per Ground Pin
$75
mA
TSTG
Storage Temperature Range
*65 to )150
_C
260
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
)150
_C
qJA
Thermal Resistance
PDIP
SOIC
TSSOP
67
96
128
_C/W
PD
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
Level 1
Oxygen Index: 30% to 35%
ESD Withstand Voltage
UL 94 V−0 @ 0.125 in
u2000
u200
u1000
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
V
$300
mA
Above VCC and Below GND at 85_C (Note 6)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow.
2. IO absolute maximum rating must observed.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
ILATCHUP
Latchup Performance
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 3) VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
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3
Min
Max
Unit
2.0
6.0
V
0
VCC
V
–55
+125
_C
0
0
0
1000
500
400
ns
MC74HC245A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
–55 to
25_C
Symbol
Parameter
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input Voltage
Vout = VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level Input Voltage
Vout = 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH |Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
Vin = VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIL |Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOL
Test Conditions
Maximum Low−Level Output
Voltage
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
IOZ
Maximum Three−State Leakage
Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
mA
ICC
Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4.0
40
160
mA
7. Information on typical parametric values and high frequency or heavy load considerations can be found in the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
–55 to
25_C
v 85_C
v 125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay,
A to B, B to A
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
55
15
13
95
70
19
16
110
80
22
19
ns
tPLZ,
tPHZ
Maximum Propagation Delay,
Direction or Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
tPZL,
tPZH
Maximum Propagation Delay,
Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
tTLH,
tTHL
Maximum Output Transition Time,
Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
Symbol
Parameter
Cin
Maximum Input Capacitance (Pin 1 or Pin 19)
−
10
10
10
pF
Cout
Maximum Three−State I/O Capacitance
(I/O in High−Impedance State)
−
15
15
15
pF
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
40
CPD
Power Dissipation Capacitance (Per Transceiver Channel) (Note 9)
pF
9. Used to determine the no−load dynamic power consumption: PD = CPD V CC2 f + I CC V CC . For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
MC74HC245A
VCC
DIRECTION
50%
GND
tf
tr
INPUT
A OR B
VCC
90%
50%
10%
GND
tPLH
OUTPUT
B OR A
VCC
OUTPUT
ENABLE
50%
GND
tPZL
tPHL
90%
50%
10%
A OR B
tTLH
tTHL
Figure 3. Switching Waveform
tPHZ
10%
VOL
90%
VOH
50%
HIGH
IMPEDANCE
Figure 4. Switching Waveform
TEST POINT
TEST POINT
OUTPUT
OUTPUT
CL*
HIGH
IMPEDANCE
50%
tPZH
A OR B
DEVICE
UNDER
TEST
tPLZ
DEVICE
UNDER
TEST
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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5
MC74HC245A
A1
2
18
A2
3
17
A3
A5
OUTPUT ENABLE
B7
9
11
DIRECTION
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
5
15
A
DATA
PORT
B2
4
16
A4
B1
1
19
Figure 7. Expanded Logic Diagram
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6
B8
B
DATA
PORT
MC74HC245A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
−A−
20
11
1
10
B
L
C
−T−
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
M
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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7
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HC245A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
−U−
L
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
http://onsemi.com
8
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HC245A
PACKAGE DIMENSIONS
SOEIAJ−20
CASE 967−01
ISSUE A
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.032
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