MC74HC245ANG

MC74HC245A Octal 3-State Noninverting Bus Transceiver High−Performance Silicon−Gate CMOS The MC74HC245A is identical in pinout to the LS245. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC245A is a 3−state noninverting transceiver that is used for 2−way asynchronous communication between data buses. The device has an active−low Output Enable pin, which is used to place the I/O ports into high−impedance states. The Direction control determines whether data flows from A to B or from B to A. http://onsemi.com SOIC−20 DW SUFFIX CASE 751D Features • • • • • • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 308 FETs or 77 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free and are RoHS Compliant LOGIC DIAGRAM A1 A2 A3 A DATA PORT A4 A5 A6 A7 A8 DIRECTION OUTPUT ENABLE PIN ASSIGNMENT DIRECTION 1 20 VCC A1 2 19 OUTPUT ENABLE A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 A8 9 12 B7 10 11 B8 GND 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 TSSOP−20 DT SUFFIX CASE 948E B1 MARKING DIAGRAMS B2 B3 20 B4 B DATA PORT B5 B6 20 HC 245A ALYWG G HC245A AWLYYWWG B7 1 B8 1 SOIC−20 1 A WL, L YY, Y WW, W G or G 19 PIN 10 = GND PIN 20 = VCC TSSOP−20 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2014 November, 2014 − Rev. 16 1 Publication Order Number: MC74HC245A/D MC74HC245A FUNCTION TABLE Control Inputs Output Enable Direction L L Data Transmitted from Bus B to Bus A L H Data Transmitted from Bus A to Bus B H X Buses Isolated (High−Impedance State) Operation X = don’t care MAXIMUM RATINGS (Note 1) Symbol Parameter VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage (Note 2) Value Unit −0.5 to +7.0 V −0.5 to VCC + 0.5 V −0.5 to VCC + 0.5 V IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±35 mA IOUT DC Output Sink Current ±35 mA ICC DC Supply Current per Supply Pin ±75 mA IGND DC Ground Current per Ground Pin ±75 mA TSTG Storage Temperature Range −65 to +150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction Temperature Under Bias +150 _C qJA Thermal Resistance SOIC TSSOP 96 128 _C/W PD Power Dissipation in Still Air at 85_C SOIC TSSOP 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD ILATCHUP Level 1 Oxygen Index: 30% to 35% ESD Withstand Voltage Latchup Performance UL 94 V−0 @ 0.125 in Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) Above VCC and Below GND at 85_C (Note 6) u2000 u200 u1000 V ±300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow. 2. IO absolute maximum rating must observed. 3. Tested to EIA/JESD22−A114−A. 4. Tested to EIA/JESD22−A115−A. 5. Tested to JESD22−C101−A. 6. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C 0 0 0 1000 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 2 MC74HC245A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC V –55 to 25_C Symbol Parameter v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High−Level Output Voltage Vin = VIH |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin = VIH |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 Vin = VIL |Iout| v 20 mA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIL |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 VOL Test Conditions Maximum Low−Level Output Voltage V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 ±0.5 ±5.0 ±10 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4.0 40 160 mA VCC V –55 to 25_C AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit v 85_C v 125_C Unit tPLH, tPHL Maximum Propagation Delay, A to B, B to A (Figures 1 and 3) 2.0 3.0 4.5 6.0 75 55 15 13 95 70 19 16 110 80 22 19 ns tPLZ, tPHZ Maximum Propagation Delay, Direction or Output Enable to A or B (Figures 2 and 4) 2.0 3.0 4.5 6.0 110 90 22 19 140 110 28 24 165 130 33 28 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to A or B (Figures 2 and 4) 2.0 3.0 4.5 6.0 110 90 22 19 140 110 28 24 165 130 33 28 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns Symbol Parameter Cin Maximum Input Capacitance (Pin 1 or Pin 19) − 10 10 10 pF Cout Maximum Three−State I/O Capacitance (I/O in High−Impedance State) − 15 15 15 pF Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Transceiver Channel) (Note 7) 7. Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . http://onsemi.com 3 40 pF MC74HC245A ORDERING INFORMATION Package Shipping† MC74HC245ADWG SOIC−20 WIDE (Pb−Free) 38 Units / Rail NLV74HC245ADWG* SOIC−20 WIDE (Pb−Free) 38 Units / Rail MC74HC245ADWR2G SOIC−20 WIDE (Pb−Free) 1000 Tape & Reel NLV74HC245ADWR2G* SOIC−20 WIDE (Pb−Free) 1000 Tape & Reel MC74HC245ADTG TSSOP−20 (Pb−Free) 75 Units / Rail NLV74HC245ADTG* TSSOP−20 (Pb−Free) 75 Units / Rail MC74HC245ADTR2G TSSOP−20 (Pb−Free) 2500 Tape & Reel NLV74HC245ADTR2G* TSSOP−20 (Pb−Free) 2500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. VCC DIRECTION 50% GND VCC tr tf INPUT A OR B VCC 90% 50% 10% tPHL A OR B 90% 50% 10% GND tPLZ A OR B HIGH IMPEDANCE 50% tPZH tPHZ 10% VOL 90% VOH 50% HIGH IMPEDANCE tTHL tTLH Figure 1. Switching Waveform Figure 2. Switching Waveform TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST 50% tPZL GND tPLH OUTPUT B OR A OUTPUT ENABLE OUTPUT CL * DEVICE UNDER TEST 1 kW CL * CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit http://onsemi.com 4 MC74HC245A A1 2 18 A2 3 17 A3 A5 OUTPUT ENABLE B7 9 11 DIRECTION B6 8 12 A8 B5 7 13 A7 B4 6 14 A6 B3 5 15 A DATA PORT B2 4 16 A4 B1 1 19 Figure 5. Expanded Logic Diagram http://onsemi.com 5 B8 B DATA PORT MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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