MC74HC373A
Octal 3-State Non-Inverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
The HC373A is the non−inverting version of the HC533A.
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SOIC−20
DW SUFFIX
CASE 751D
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
Features
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MARKING DIAGRAMS
20
20
HC
373A
ALYWG
G
HC373A
AWLYYWWG
1
1
SOIC−20
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
3
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
11
1
Q0
Q1
Q2
Q3
Q4
NONINVERTING
OUTPUTS
TSSOP−20
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Q5
Output
Enable
L
L
L
H
Q6
Q7
PIN 20 = VCC
PIN 10 = GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LATCH
ENABLE
Output
Latch
Enable
H
H
L
X
D
H
L
X
X
Q
H
L
No Change
Z
X = Don’t Care
Z = High Impedance
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 15
1
Publication Order Number:
MC74HC373A/D
MC74HC373A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Design Criteria
Value
Units
Internal Gate Count*
46.5
ea
Internal Gate Propagation Delay
1.5
ns
5.0
mW
0.0075
pJ
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
–0.5 to +7.0
V
Vin
DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
–65 to +150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC, SSOP or TSSOP Package)
SOIC Package†
TSSOP Package†
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
–55
+125
_C
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74HC373A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VIH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
Vout = VCC – 0.1 V
|Iout| v 20 mA
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V
|Iout| v 20 mA
VOH
Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VIH
VOL
Maximum Low−Level Output
Voltage
Vin = VIL
|Iout| v 20 mA
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VIL
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
–55 to 25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
v 85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
v 125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
Unit
V
V
V
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
±0.1
±1.0
±1.0
mA
IOZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±0.5
±5.0
±10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4.0
40
160
mA
v 125_C
190
130
38
32
210
140
42
36
225
150
45
38
225
150
45
38
90
32
18
15
10
15
Unit
ns
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
tPLH
tPHL
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Parameter
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
tPLZ
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
tPZL
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
Cin
Cout
Maximum Input Capacitance
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
Guaranteed Limit
–55 to 25_C
125
80
25
21
140
90
28
24
150
100
30
26
150
100
30
26
60
23
12
10
10
15
CPD
Power Dissipation Capacitance (Per Enabled Output)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .
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3
v 85_C
155
110
31
26
175
120
35
30
190
125
38
33
190
125
38
33
75
27
15
13
10
15
Typical @ 25°C, VCC = 5.0 V
36
ns
ns
ns
ns
pF
pF
pF
MC74HC373A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Parameter
Symbol
Figure
VCC
Volts
v 85_C
–55 to 25_C
Min
Max
Min
v 125_C
Max
Min
Max
Unit
tsu
Minimum Setup Time, Input D to Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
th
Minimum Hold Time, Latch Enable to Input D
4
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
50
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
tr
tf
INPUT D
tw
VCC
90%
50%
10%
LATCH ENABLE
GND
tPLH
GND
tPHL
Q
tTLH
50%
tTHL
Figure 1.
OUTPUT
ENABLE
VCC
GND
tPLZ
VALID
VCC
HIGH
IMPEDANCE
50%
tPZH
Q
Figure 2.
50%
tPZL
Q
tPHL
tPLH
90%
50%
10%
Q
VCC
50%
10%
VOL
90%
VOH
INPUT D
tsu
tPHZ
1.3 V
50%
GND
th
VCC
LATCH ENABLE
50%
GND
HIGH
IMPEDANCE
Figure 3.
Figure 4.
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4
MC74HC373A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
D0
3
Figure 6.
D1
4
D
Q
D2
7
D
LE
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
OUTPUT
Q
D3
8
D
LE
Q
D4
13
D
LE
Q
D5
14
D
LE
Q
D6
17
D
LE
Q
D7
18
D
LE
Q
D
LE
Q
LE
11
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
Figure 7. Expanded Logic Diagram
ORDERING INFORMATION
Package
Shipping†
MC74HC373ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HC373ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Units / Reel
MC74HC373ADTG
TSSOP−20
(Pb−Free)
75 Units / Rail
MC74HC373ADTR2G
TSSOP−20
(Pb−Free)
2500 Units / Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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onsemi,
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and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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