MC74HC390AFELG

MC74HC390A Dual 4-Stage Binary Ripple Counter with ÷ 2 and ÷ 5 Sections High−Performance Silicon−Gate CMOS http://onsemi.com The MC74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4−bit counters, each composed of a divide−by−two and a divide−by−five section. The divide−by−two and divide−by−five counters have separate clock inputs, and can be cascaded to implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter. Flip−flops internal to the counters are triggered by high−to−low transitions of the clock input. A separate, asynchronous reset is provided for each 4−bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A. SOIC−16 D SUFFIX CASE 751B PIN ASSIGNMENT CLOCK Aa 1 16 VCC RESET a 2 15 CLOCK Ab QAa 3 14 RESET b CLOCK Ba 4 13 QAb QBa 5 12 CLOCK Bb QCa 6 11 QBb QDa 7 10 QCb GND 8 9 QDb Features • • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No 7 A Chip Complexity: 244 FETs or 61 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant TSSOP−16 DT SUFFIX CASE 948F MARKING DIAGRAMS 16 16 HC 390A ALYWG G HC390AG AWLYWW 1 1 SOIC−16 A L, WL Y, YY W, WW G or G TSSOP−16 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) CLOCK A 1, 15 ÷2 COUNTER 3, 13 FUNCTION TABLE QA Clock A B Reset Action X X H X L Reset ÷ 2 and ÷ 5 Increment ÷2 Increment ÷5 5, 11 CLOCK B RESET 4, 12 ÷5 COUNTER QB 6, 10 QC 7, 9 QD X PIN 16 = VCC PIN 8 = GND 2, 14 August, 2014 − Rev. 7 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Figure 1. Logic Diagram © Semiconductor Components Industries, LLC, 2014 L 1 Publication Order Number: MC74HC390A/D MC74HC390A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 V DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) VCC DC Supply Voltage (Referenced to GND) Vin Vout –0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA mA Iout DC Output Current, per Pin ±25 ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature –65 to +150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds SOIC or TSSOP Package SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C 0 0 0 0 1000 600 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V –55 to 25_C v85_C v125_C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Vin = VIH or VIL VOL Maximum Low−Level Output Voltage |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA http://onsemi.com 2 V MC74HC390A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (continued) Guaranteed Limit Symbol Parameter Test Conditions VCC V –55 to 25_C v85_C v125_C Unit Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4 40 160 mA AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns) Guaranteed Limit Parameter Symbol VCC V –55 to 25_C v85_C v125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 3) 2.0 3.0 4.5 6.0 10 15 30 50 9 14 28 45 8 12 25 40 MHz tPLH, tPHL Maximum Propagation Delay, Clock A to QA (Figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 24 20 80 45 30 26 90 50 36 31 ns tPLH, tPHL Maximum Propagation Delay, Clock A to QC (QA connected to Clock B) (Figures 1 and 3) 2.0 3.0 4.5 6.0 200 160 58 49 250 185 65 62 300 210 70 68 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QB (Figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 26 22 80 45 33 28 90 50 39 33 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QC (Figures 1 and 3) 2.0 3.0 4.5 6.0 90 56 37 31 105 70 46 39 180 100 56 48 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QD (Figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 26 22 80 45 33 28 90 50 39 33 ns tPHL Maximum Propagation Delay, Reset to any Q (Figures 2 and 3) 2.0 3.0 4.5 6.0 80 48 30 26 95 65 38 33 110 75 44 39 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns − 10 10 10 pF Cin Maximum Input Capacitance Typical @ 25°C, VCC = 5.0 V CPD 35 Power Dissipation Capacitance (Per Counter)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC http://onsemi.com 3 2f + ICC VCC . pF MC74HC390A TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V –55 to 25_C v85_C v125_C Unit trec Minimum Recovery Time, Reset Inactive to Clock A or Clock B (Figure 3) 2.0 3.0 4.5 6.0 25 15 10 9 30 20 13 11 40 30 15 13 ns tw Minimum Pulse Width, Clock A, Clock B (Figure 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns tw Minimum Pulse Width, Reset (Figure 3) 2.0 3.0 4.5 6.0 75 27 20 18 95 32 24 22 110 36 30 28 ns Maximum Input Rise and Fall Times (Figure 2) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns tf, tf PIN DESCRIPTIONS INPUTS Clock A (Pins 1, 15) and Clock B (Pins 4, 15) OUTPUTS QA (Pins 3, 13) Clock A is the clock input to the ÷ 2 counter; Clock B is the clock input to the ÷ 5 counter. The internal flip−flops are toggled by high−to−low transitions of the clock input. Output of the ÷ 2 counter. QB, QC, QD (Pins 5, 6, 7, 9, 10, 11) Outputs of the ÷ 5 counter. QD is the most significant bit. QA is the least significant bit when the counter is connected for BCD output as in Figure 5. QB is the least significant bit when the counter is operating in the bi−quinary mode as in Figure 6. CONTROL INPUTS Reset (Pins 2, 14) Asynchronous reset. A high at the Reset input prevents counting, resets the internal flip−flops, and forces QA through QD low. SWITCHING WAVEFORMS CLOCK tf 90% 50% 10% 10% tr tw VCC VCC GND GND tw tPHL 1/fmax tPLH Q 50% RESET Q tPHL 90% 50% 10% 50% trec tTLH tTHL VCC 50% CLOCK GND Figure 2. Figure 3. http://onsemi.com 4 MC74HC390A TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 4. EXPANDED LOGIC DIAGRAM 1, 15 CLOCK A Q C D 4, 12 CLOCK B R R 5, 11 Q QB Q C D QA Q C D 3, 13 Q R Q 6, 10 Q C Q 7, 9 Q D C D R 2, 14 RESET TIMING DIAGRAM (QA Connected to Clock B) 0 1 2 3 4 5 6 7 8 9 CLOCK A RESET QA QB QC QD http://onsemi.com 5 0 1 2 3 4 5 6 MC74HC390A APPLICATIONS INFORMATION Each half of the MC54/74HC390A has independent ÷ 2 and ÷ 5 sections (except for the Reset function). The ÷ 2 and ÷ 5 counters can be connected to give BCD or bi−quinary (2−5) count sequences. If Output QA is connected to the Clock B input (Figure 4), a decade divider with BCD output is obtained. The function table for the BCD count sequence is given in Table 1. To obtain a bi−quinary count sequence, the input signals connected to the Clock B input, and output QD is connected to the Clock A input (Figure 6). QA provides a 50% duty cycle output. The bi−quinary count sequence function table is given in Table 2. Table 1. BCD Count Sequence* Table 2. Bi−Quinary Count Sequence** Output QD Count QC 0 L L 1 L L 2 L L 3 L L 4 L H 5 L H 6 L H 7 L H 8 H L 9 H L *QA connected to Clock B input. Output QB QA Count QA QD QC QB L L H H L L H H L L L H L H L H L H L H 0 1 2 3 4 8 9 10 11 12 L L L L L H H H H H L L L L H L L L L H L L H H L L L H H L L H L H L L H L H L ** QD connected to Clock A input. CONNECTION DIAGRAMS 1, 15 CLOCK A ÷2 COUNTER 5, 11 4, 12 CLOCK B 3, 13 ÷5 COUNTER 6, 10 7, 9 1, 15 QA CLOCK A QB CLOCK B QC ÷5 COUNTER QD 3, 13 QA 5, 11 QB 6, 10 7, 9 QC QD 2, 14 2, 14 RESET 4, 12 ÷2 COUNTER RESET Figure 5. BCD Count Figure 6. Bi-Quinary Count ORDERING INFORMATION Package Shipping† MC74HC390ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC390ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74HC390ADTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel NLV74HC390ADR2G* SOIC−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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