MC74HC4020AFELG

MC74HC4020A 14-Stage Binary Ripple Counter High−Performance Silicon−Gate CMOS The MC74C4020A is identical in pinout to the standard CMOS MC14020B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 14 master−slave flip−flops with 12 stages brought out to pins. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. Reset is asynchronous and active−high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4020A for some designs. http://onsemi.com SOIC−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F PIN ASSIGNMENT VCC Q11 Q10 Q8 Q9 16 15 14 13 12 Reset Clock 11 Q1 10 9 Features • • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 398 FETs or 99.5 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 1 2 3 4 5 6 7 8 Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND 16−Lead Package (Top View) MARKING DIAGRAMS 16 16 HC40 20A ALYWG G HC4020AG AWLYWW 1 9 7 5 4 Clock 10 6 13 12 14 15 1 2 3 Reset 11 1 SOIC−16 Q1 Q4 A L, WL Y, YY W, WW G or G Q5 Q6 Q7 Q8 Q9 TSSOP−16 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Q10 FUNCTION TABLE Q11 Q12 Clock Reset X L L H Q13 Q14 Pin 16 = VCC Pin 8 = GND Figure 1. Logic Diagram Output State No Change Advance to Next State All Outputs Are Low ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 8 1 Publication Order Number: MC74HC4020A/D MC74HC4020A MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 V DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air 500 450 mW Tstg Storage Temperature Range –65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds SOIC or TSSOP Package SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C 0 0 0 0 1000 600 500 400 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Figure 2) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA Vin =VIH or VIL VOL Maximum Low−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20mA |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA Vin = VIH or VIL V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0mA 6.0 4 40 160 mA http://onsemi.com 2 MC74HC4020A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 2 and 5) 2.0 3.0 4.5 6.0 10 15 30 50 9.0 14 28 50 8.0 12 25 40 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q1* (Figures 4 and 5) 2.0 3.0 4.5 6.0 96 63 31 25 106 71 36 30 115 88 40 35 ns tPHL Maximum Propagation Delay, Reset to Any Q (Figures 3 and 5) 2.0 3.0 4.5 6.0 65 30 30 26 72 36 35 32 90 40 40 35 ns tPLH, tPHL Maximum Propagation Delay, Qn to Qn+1 (Figures 4 and 5) 2.0 3.0 4.5 6.0 69 40 17 14 80 45 21 15 90 50 28 22 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 2 and 5) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns 10 10 10 pF Cin Maximum Input Capacitance * For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: VCC = 2.0 V: tP = [93.7 + 59.3 (n−1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n−1)] ns VCC = 3.0 V: tP = [61.5 + 34.4 (n−1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n−1)] ns Typical @ 25°C, VCC = 5.0 V CPD 38 Power Dissipation Capacitance (Per Package)* pF TIMING REQUIREMENTS (Input tr = tf = 6 ns) VCC V Guaranteed Limit −55 to 25°C ≤85°C ≤125°C Unit trec Minimum Recovery Time, Reset Inactive to Clock (Figure 3) 2.0 3.0 4.5 6.0 30 20 5 4 40 25 8 6 50 30 12 9 ns tw Minimum Pulse Width, Clock (Figure 2) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns tw Minimum Pulse Width, Reset (Figure 3) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns Maximum Input Rise and Fall Times (Figure 2) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns Parameter Symbol tr, tf http://onsemi.com 3 MC74HC4020A PIN DESCRIPTIONS INPUTS Clock (Pin 10) OUTPUTS Q1, Q4—Q14 (Pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3) Negative−edge triggering clock input. A high−to−low transition on this input advances the state of the counter. Active−high outputs. Each Qn output divides the Clock input frequency by 2N. Reset (Pin 11) Active−high reset. A high level applied to this input asynchronously resets the counter to its zero state, thus forcing all Q outputs low. SWITCHING WAVEFORMS tf tr VCC 90% 50% 10% Clock Clock VCC tw 1/fMAX Reset tPHL tPLH GND trec GND tw Q1 50% 90% 50% 10% VCC 50% GND tPHL tTLH Any Q tTHL Figure 2. 50% Figure 3. TEST POINT VCC Qn OUTPUT 50% DEVICE UNDER TEST GND tPLH Qn+1 tPHL CL* 50% *Includes all probe and jig capacitance Figure 4. Figure 5. Test Circuit http://onsemi.com 4 MC74HC4020A Q1 Q4 9 Clock 10 Q12 Q13 Q14 1 2 3 5 C Q C Q C Q C Q C Q C C Q C Q C Q C Q C Q C R Reset Q5 7 Q R 11 Q6 = Pin 4 Q7 = Pin 6 Q8 = Pin 13 Q9 = Pin 12 Q10 = Pin 14 Q11 = Pin 15 VCC = Pin 16 GND = Pin 8 Figure 6. Expanded Logic Diagram 1 2 4 8 16 32 64 128 256 Clock Reset Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q12 Q13 Q14 Figure 7. Timing Diagram http://onsemi.com 5 512 1024 2048 4096 8192 16384 MC74HC4020A APPLICATIONS INFORMATION Time−Base Generator feeds the HC4020A. Selecting outputs Q5, Q10, Q11, and Q12 causes a reset every 3600 clocks. The HC20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute. A 60Hz sinewave obtained through a 1.0 Megohm resistor connected directly to a standard 120 Vac power line is applied to the input of the MC54/74HC14A, Schmitt-trigger inverter. The HC14A squares−up the input waveform and VCC VCC 1/6 of HC14A 1.0M HC4020A Clock 12 ≥20pF 120Vac 60Hz 13 Q5 Q10 10 Q11 1/2 HC20 8 1 2 4 5 1/2 HC20 6 1.0 Pulse/Minute Output 9 Q12 NOTE: Ground MUST be isolated by a transformer or opto−isolator for safety reasons. Figure 8. Time−Base Generator ORDERING INFORMATION Package Shipping† MC74HC4020ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC4020ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74HC4020ADTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel NLV74HC4020ADTR2G* TSSOP−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative