MC74HC4538AF

MC74HC4538A Dual Precision Monostable Multivibrator (Retriggerable, Resettable) The MC74HC4538A is identical in pinout to the MC14538B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse, and produces a precision output pulse over a wide range of pulse widths. Because the device has conditioned trigger inputs, there are no trigger−input rise and fall time restrictions. The output pulse width is determined by the external timing components, Rx and Cx. The device has a reset function which forces the Q output low and the Q output high, regardless of the state of the output pulse circuitry. Features • Unlimited Rise and Fall Times Allowed on the Trigger Inputs • Output Pulse is Independent of the Trigger Pulse Width • ± 10% Guaranteed Pulse Width Variation from Part to Part • • • • • • • • • (Using the Same Test Jig) Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 145 FETs or 36 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free and are RoHS Compliant http://onsemi.com SOIC−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F PIN ASSIGNMENT GND 1 16 CX1/RX1 2 15 GND RESET 1 3 14 CX2/RX2 A1 4 13 RESET 2 B1 5 12 A2 Q1 6 11 B2 Q1 7 10 Q2 GND 8 9 Q2 VCC MARKING DIAGRAMS 16 HC4538AG AWLYWW 1 SOIC−16 16 HC45 38A ALYWG G 1 TSSOP−16 A L, WL Y, YY W, WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 15 1 Publication Order Number: MC74HC4538A/D MC74HC4538A FUNCTION TABLE Inputs Reset A Outputs B Q Q H H H L H H X H L X Not Triggered Not Triggered H H L,H, L H L,H, Not Triggered Not Triggered L X X X X L H Not Triggered CX 1 RX 1 VCC 1 TRIGGER INPUTS A1 B1 RESET 1 2 4 6 5 7 Q1 Q1 PIN 16 = VCC PIN 8 = GND RX AND CX ARE EXTERNAL COMPONENTS PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND 3 CX 2 RX 2 VCC 15 14 TRIGGER INPUTS A2 B2 RESET 2 12 10 11 9 Q2 Q2 13 Figure 1. Logic Diagram ORDERING INFORMATION Package Shipping† MC74HC4538ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC4538ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel NLV74HC4538ADR2G* SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74HC4538ADTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel NLVHC4538ADTR2G* TSSOP−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable http://onsemi.com 2 MC74HC4538A MAXIMUM RATINGS Symbol VCC Parameter Value Unit −0.5 to +7.0 V −0.5 ≤ VI ≤ VCC + 0.5 V −0.5 ≤ VO ≤ VCC + 0.5 V ±20 ±30 mA ±25 mA DC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current (Note 1) A, B, Reset CX, RX IO DC Output Sink Current ±25 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 _C TL Lead temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction temperature under Bias +150 _C qJA Thermal resistance SOIC TSSOP 112 148 _C/W PD Power Dissipation in Still Air at 85_C SOIC TSSOP 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup Level 1 Oxygen Index: 30% − 35% ESD Withstand Voltage Latchup Performance UL−94−VO (0.125 in) Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85_C (Note 5) > 2000 > 100 > 500 V ±300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 6) External Timing Resistor Cx External Timing Capacitor Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 0 0 0 − 1000 500 400 No Limit ns VCC < 4.5 V VCC ≥ 4.5 V 1.0 2.0 † † kW 0 † mF A or B (Figure 4) Rx Min Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. †The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due to board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 mF/1.0 MW. Values of Cx > 1.0 mF may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for Rx > 1.0 MW. 6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. http://onsemi.com 3 MC74HC4538A DC CHARACTERISTICS Guaranteed Limits Symbol Parameter ≤ 85_C –55 to 25_C Test Conditions VCC V Min 1.5 3.15 4.2 Typ Max Min Typ ≤ 125_C Max VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 2.0 4.5 6.0 VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 2.0 4.5 6.0 VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 Vin = VIH or VIL |Iout| ≤ − 4.0 mA |Iout| ≤ − 5.2 mA VOL Maximum Low−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20 mA 1.5 3.15 4.2 Min Typ Max 1.5 3.15 4.2 0.5 1.35 1.8 0.5 1.35 1.8 Unit V 0.5 1.35 1.8 V V 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| ≤ 4.0 mA |Iout| ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 V Iin Maximum Input Leakage Current (A, B, Reset) Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA Iin Maximum Input Leakage Current (Rx, Cx) Vin = VCC or GND 6.0 ± 50 ±500 ±500 nA ICC Maximum Quiescent Supply Current (per package) Standby State Vin = VCC or GND Q1 and Q2 = Low Iout = 0 mA 6.0 130 220 350 mA Maximum Supply Current (per package) Active State Vin = VCC or GND Q1 and Q2 = High Iout = 0 mA Pins 2 and 14 = 0.5 VCC ICC 6.0 25_C –45_C to 85_C 400 600 –55_C to 125_C 800 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://onsemi.com 4 MC74HC4538A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limits VCC V Parameter Symbol ≤ 85_C –55 to 25_C Min Max Min Max ≤ 125_C Min Max Unit tPLH Maximum Propagation Delay Input A or B to Q (Figures 5 and 7) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPHL Maximum Propagation Delay Input A or B to NQ (Figures 5 and 7) 2.0 4.5 6.0 195 39 33 245 49 42 295 59 50 ns tPHL Maximum Propagation Delay Reset to Q (Figures 6 and 7) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPLH Maximum Propagation Delay Reset to NQ (Figures 6 and 7) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 6 and 7) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns − 10 25 10 25 10 25 pF Cin Maximum Input Capacitance (A. B, Reset) (Cx, Rx) Typical @ 25°C, VCC = 5.0 V CPD 150 Power Dissipation Capacitance (per Multivibrator)* *Used to determine the no−load dynamic power consumption: PD = CPD VCC 2f pF + ICC VCC . TIMING CHARACTERISTICS (Input tr = tf = 6.0 ns) Guaranteed Limits Parameter Symbol ≤ 85_C –55 to 25_C Min Max Min Max ≤ 125_C Min Max Unit trr Minimum Retrigger Time, Input A or B (Figure 6) (Note 7) 2.0 4.5 6.0 − − − − − − trec Minimum Recovery Time, Inactive to A or B (Figure 6) 2.0 4.5 6.0 0 0 0 0 0 0 0 0 0 ns tw Minimum Pulse Width, Input A or B (Figure 5) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tw Minimum Pulse Width, Reset (Figure 6) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Maximum Input Rise and Fall Times, Reset (Figure 6) 2.0 4.5 6.0 A or B (Figure 6) 2.0 4.5 6.0 tr, tf 7. VCC V t rr(ns) + V CC (volts) C x (pF) 30.5 http://onsemi.com 5 1000 500 400 ns 1000 500 400 No Limit 1000 500 400 ns MC74HC4538A OUTPUT PULSE WIDTH CHARACTERISTICS (Rx = 10 kW, Cx = 0.1 mF, CL = 50 pF) Conditions Symbol Parameter Guaranteed Limits Timing Components Output Pulse Width (Note 8) (Figures 5 and 6) τ Pulse Width Match Between Circuits in the same Package Rx = 10 kW, Cx = 0.1 mF ≤ 85_C –55 to 25_C VCC V ≤ 125_C Min Max Min Max Min Max Unit 0.63 0.77 0.6 0.8 0.59 0.81 ms 5.0 Pulse Width Match Variation (Part to Part) (Note 10) ±5.0 % ±10 % OUTPUT PULSE WIDTH CHARACTERISTICS (Rx = 100 kW, Cx = 1 nF, CL = 50 pF) Conditions Symbol Parameter Timing Components VCC V Output Pulse Width (Note 9) τ Pulse Width Match Between Circuits in the same Package Pulse Width Match Variation (Part to Part) (Note 10) Rx = 100 kW, Cx = 1 nF 5.0 Guaranteed Limits Ambient Temperature Min Typ Max Unit 25°C − 79 − ms −55 to 125°C −5.0 − +5.0 % −55 to 125°C −10 − +10 % − Temperature Variance −55 to 125°C − +0.05 − ms/°C − Power Supply Variance −55 to 125°C − −8.0 − ms/V 8. τ = kRxCx and k = 0.7 for the output pulse width corresponding to Rx = 10 kW, Cx = 0.1 mF. 9. τ = kRxCx and k = 0.79 for the output pulse width corresponding to Rx = 100 kW, Cx = 1 nF. 10. Pulse width match variation between ICs (part−to−part) is defined with identical Rx, Cx, VCC and a specific temperature. http://onsemi.com 6 MC74HC4538A 0.70 10 s TA = 25°C OUTPUT PULSE WIDTH (τ) k, OUTPUT PULSE WIDTH CONSTANT (TYPICAL) TYPICAL CHARACTERISTICS 0.65 0.60 0.55 0.50 1 2 3 4 5 6 VCC, POWER SUPPLY VOLTAGE (VOLTS) 1s VCC = 5 V, TA = 25°C 100 ms 10 ms 1 ms 100 ms 1 MW 10 ms 100 kW 1 ms 10 kW 1 kW 100 ns 0.00001 0.0001 7 Figure 2. Typical Output Pulse Width Constant, k, versus Supply Voltage (For output pulse widths > 100 ms: τ = kRxCx) 0.001 0.01 0.1 CAPACITANCE (mF) 1 10 Figure 3. Output Pulse Width versus Timing Capacitance OUTPUT PULSE WIDTH (τ) (NORMALIZED TO 5 V NUMBER) 1.30 TA = 25°C Rx = 1 MW Cx = 0.1 mF 1.20 1.10 1.00 Rx = 100 kW Cx = 1000 pF 0.90 0.80 1 2 3 4 5 6 VCC, POWER SUPPLY VOLTAGE (VOLTS) 7 Figure 4. Normalized Output Pulse Width versus Power Supply Voltage 1.025 1.05 OUTPUT PULSE WIDTH (τ) (NORMALIZED TO 25_C NUMBER) OUTPUT PULSE WIDTH (τ) (NORMALIZED TO 25_C NUMBER) 1.075 VCC = 6 V 1.025 1.0 0.975 VCC = 3 V 0.95 −75 −50 −25 0 25 50 75 100 125 VCC = 5.5 V 1.02 VCC = 5 V 1.015 VCC = 4.5 V 1.01 1.005 1.00 25 150 TA, AMBIENT TEMPERATURE (°C) 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) Figure 5. Normalized Output Pulse Width versus Power Supply Voltage Figure 6. Normalized Output Pulse Width versus Power Supply Voltage http://onsemi.com 7 MC74HC4538A tw(H) VCC 50% A GND tw(L) VCC B 50% GND τ tPLH τ tPLH 50% Q τ tPHL τ tPHL Q 50% Figure 7. Switching Waveform tr tf VCC 90% 10% A GND trr VCC 50% GND B tf tf GND trec τ + trr tPHL 90% 50% 50% 10% Q tTHL Q 10% tw(L) tTLH VCC 90% 50% RESET tPLH 90% 10% 50% Figure 8. Switching Waveform TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 9. Test Circuit http://onsemi.com 8 (RETRIGGERED PULSE) MC74HC4538A PIN DESCRIPTIONS INPUTS capacitors (see the Block Diagram). Polystyrene capacitors are recommended for optimum pulse width control. Electrolytic capacitors are not recommended due to high leakages associated with these type capacitors. A1, A2 (Pins 4, 12) Positive−edge trigger inputs. A rising−edge signal on either of these pins triggers the corresponding multivibrator when there is a high level on the B1 or B2 input. GND (Pins 1 and 15) External ground. The external timing capacitors discharge to ground through these pins. B1, B2 (Pins 5, 11) Negative−edge trigger inputs. A falling−edge signal on either of these pins triggers the corresponding multivibrator when there is a low level on the A1 or A2 input. OUTPUTS Q1, Q2 (Pins 6, 10) Reset 1, Reset 2 (Pins 3, 13) Noninverted monostable outputs. These pins (normally low) pulse high when the multivibrator is triggered at either the A or the B input. The width of the pulse is determined by the external timing components, RX and CX. Reset inputs (active low). When a low level is applied to one of these pins, the Q output of the corresponding multivibrator is reset to a low level and the Q output is set to a high level. Q1, Q2 (Pins 7, 9) CX1/RX1 and CX2/RX2 (Pins 2 and 14) Inverted monostable outputs. These pins (normally high) pulse low when the multivibrator is triggered at either the A or the B input. These outputs are the inverse of Q1 and Q2. External timing components. These pins are tied to the common points of the external timing resistors and RxCx UPPER REFERENCE CIRCUIT − + Vre, UPPER VCC VCC OUTPUT LATCH LOWER REFERENCE CIRCUIT M1 2 kW − + M2 Q Vre, LOWER M3 Q TRIGGER CONTROL CIRCUIT A C CB B Q TRIGGER CONTROL RESET CIRCUIT R RESET POWER ON RESET RESET LATCH Figure 10. Logic Detail (1/2 the Device) http://onsemi.com 9 MC74HC4538A CIRCUIT OPERATION TRIGGER OPERATION Figure 11 shows the HC4538A configured in the retriggerable mode. Briefly, the device operates as follows (refer to Figure 10): In the quiescent state, the external timing capacitor, Cx, is charged to VCC. When a trigger occurs, the Q output goes high and Cx discharges quickly to the lower reference voltage (Vref Lower [ 1/3 VCC). Cx then charges, through Rx, back up to the upper reference voltage (Vref Upper [ 2/3 VCC), at which point the one−shot has timed out and the Q output goes low. The following, more detailed description of the circuit operation refers to both the logic detail (Figure 10) and the timing diagram (Figure 11). The HC4538A is triggered by either a rising−edge signal at input A (#7) or a falling−edge signal at input B (#8), with the unused trigger input and the Reset input held at the voltage levels shown in the Function Table. Either trigger signal will cause the output of the trigger−control circuit to go high (#9). The trigger−control circuit going high simultaneously initiates two events. First, the output latch goes low, thus taking the Q output of the HC4538A to a high state (#10). Second, transistor M3 is turned on, which allows the external timing capacitor, Cx, to rapidly discharge toward ground (#11). (Note that the voltage across Cx appears at the input of both the upper and lower reference circuit comparator). When Cx discharges to the reference voltage of the lower reference circuit (#12), the outputs of both reference circuits will be high (#13). The trigger−control reset circuit goes high, resetting the trigger−control circuit flip−flop to a low state (#14). This turns transistor M3 off again, allowing Cx to begin to charge back up toward VCC, with a time constant t = RxCx (#15). Once the voltage across Cx charges to above the lower reference voltage, the lower reference circuit will go low allowing the monostable multivibrator to be retriggered. QUIESCENT STATE In the quiescent state, before an input trigger appears, the output latch is high and the reset latch is high (#1 in Figure 11). Thus the Q output (pin 6 or 10) of the monostable multivibrator is low (#2, Figure 11). The output of the trigger−control circuit is low (#3), and transistors M1, M2, and M3 are turned off. The external timing capacitor, Cx, is charged to VCC (#4), and both the upper and lower reference circuit has a low output (#5). In addition, the output of the trigger−control reset circuit is low. QUIESCENT STATE TRIGGER CYCLE (A INPUT) TRIGGER CYCLE (B INPUT) RESET RETRIGGER trr 7 TRIGGER INPUT A (PIN 4 OR 12) TRIGGER INPUT B (PIN 5 OR 11) 8 24 9 TRIGGER-CONTROL CIRCUIT OUTPUT 3 14 11 4 RX/CX INPUT (PIN 2 OR 14) 15 21 17 23 12 Vref LOWER UPPER REFERENCE CIRCUIT 5 LOWER REFERENCE CIRCUIT 6 Vref UPPER 13 25 18 13 16 RESET INPUT (PIN 3 OR 13) 20 1 RESET LATCH 22 10 Q OUTPUT (PIN 6 OR 10) 2 19 τ τ Figure 11. Timing Diagram http://onsemi.com 10 τ + trr MC74HC4538A occurs, the output of the reset latch goes low (#22), turning on transistor M1. Thus Cx is allowed to quickly charge up to VCC (#23) to await the next trigger signal. On power up of the HC4538A the power−on reset circuit will be high causing a reset condition. This will prevent the trigger−control circuit from accepting a trigger input during this state. The HC4538A’s Q outputs are low and the Q not outputs are high. When Cx charges up to the reference voltage of the upper reference circuit (#17), the output of the upper reference circuit goes low (#18). This causes the output latch to toggle, taking the Q output of the HC4538A to a low state (#19), and completing the time−out cycle. POWER−DOWN CONSIDERATIONS Large values of Cx may cause problems when powering down the HC4538A because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from VCC through the input protection diodes at pin 2 or pin 14. Current through the protection diodes must be limited to 30 mA; therefore, the turn−off time of the VCC power supply must not be faster than t = VCCCx /(30 mA). For example, if VCC = 5.0 V and Cx = 15 mF, the VCC supply must turn off no faster than t = (5.0 V)(15 mF)/30 mA = 2.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero volts occurs, the HC4538A may sustain damage. To avoid this possibility, use an external damping diode, Dx, connected as shown in Figure 12. Best results can be achieved if diode Dx is chosen to be a germanium or Schottky type diode able to withstand large current surges. RETRIGGER OPERATION When used in the retriggerable mode (Figure 13), the HC4538A may be retriggered during timing out of the output pulse at any time after the trigger−control circuit flip−flop has been reset (#24), and the voltage across Cx is above the lower reference voltage. As long as the Cx voltage is below the lower reference voltage, the reset of the flip−flop is high, disabling any trigger pulse. This prevents M3 from turning on during this period resulting in an output pulse width that is predictable. The amount of undershoot voltage on RxCx during the trigger mode is a function of loop delay, M3 conductivity, and VDD. Minimum retrigger time, trr (Figure 7), is a function of 1) time to discharge Rx Cx from VDD to lower reference voltage (Tdischarge); 2) loop delay (Tdelay); 3) time to charge Rx Cx from the undershoot voltage back to the lower reference voltage (Tcharge). Figure 14 shows the device configured in the non−retriggerable mode. For additional information, please see Application Note (AN1558/D) titled Characterization of Retrigger Time in the HC4538A Dual Precision Monostable Multivibrator. RESET AND POWER ON RESET OPERATION A low voltage applied to the Reset pin always forces the Q output of the HC4538A to a low state. The timing diagram illustrates the case in which reset occurs (#20) while Cx is charging up toward the reference voltage of the upper reference circuit (#21). When a reset DX CX VCC RX Q A B Q RESET Figure 12. Discharge Protection During Power Down http://onsemi.com 11 MC74HC4538A TYPICAL APPLICATIONS CX RISING−EDGE TRIGGER RX CX RX RISING−EDGE TRIGGER VCC Q A B VCC Q A Q B Q B = VCC RESET = VCC RESET = VCC CX RX CX FALLING−EDGE TRIGGER VCC A = GND VCC Q Q B RX A B Q Q FALLING−EDGE TRIGGER RESET = VCC RESET = VCC Figure 13. Retriggerable Monostable Circuitry Figure 14. Non−retriggerable Monostable Circuitry GND N/C A = GND VCC RX CX Q N/C B Q RESET N/C Figure 15. Connection of Unused Section ONE−SHOT SELECTION GUIDE 100 ns MC14528B MC14536B MC14538B MC14541B HC4538A* 1 ms 10 ms 100 ms 1 ms 10 ms 100 ms 1 s 10 s 23 HR 5 MIN *Limited operating voltage (2 −6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE http://onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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