MC74HC540ADWR2

MC74HC540A Octal 3-State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS The MC74HC540A is identical in pinout to the LS540. The device inputs are compatible with Standard CMOS outputs. External pull−up resistors make them compatible with LSTTL outputs. The HC540A is an octal inverting buffer/line driver/line receiver designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed active−low output enables. The HC540A is similar in function to the HC541A, which has noninverting outputs. MARKING DIAGRAMS 20 Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7 A Requirements Chip Complexity: 124 FETs or 31 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant 20 PDIP−20 N SUFFIX CASE 738 1 MC74HC540AN AWLYYWWG 1 20 SOIC−20 DW SUFFIX CASE 751D 20 Features • • • • • • • • http://onsemi.com 1 74HC540A AWLYYWWG 1 20 HC 540A ALYWG G TSSOP−20 DT SUFFIX CASE 948E 20 1 1 20 SOEIAJ−20 F SUFFIX CASE 967 1 20 1 A WL, L YY, Y WW, W G or G 74HC540A AWLYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 10 1 Publication Order Number: MC74HC540A/D MC74HC540A VCC OE2 20 19 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 FUNCTION TABLE Inputs 1 2 3 4 5 6 7 8 9 10 OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND A2 A3 Data Inputs A4 A5 A6 A7 A8 Output Enables OE1 OE2 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 1 OE2 A L L H X L L X H L H X X Output Y H L Z Z Z = High Impedance X = Don’t Care Figure 1. Pinout: 20−Lead Packages (Top View) A1 OE1 Y1 Y2 Y3 Y4 Y5 Inverting Outputs Y6 Y7 Y8 PIN 20 = VCC PIN 10 = GND 19 Figure 2. Logic Diagram ORDERING INFORMATION Package Shipping† PDIP−20 (Pb−Free) 18 Units / Rail MC74HC540ADWG SOIC−20 WIDE (Pb−Free) 38 Units / Rail MC74HC540ADWR2G SOIC−20 WIDE (Pb−Free) 1000 Tape & Reel MC74HC540ADTR2G TSSOP−20* 2500 Tape & Reel MC74HC540AFG SOEIAJ−20 (Pb−Free) 40 Units / Rail MC74HC540AFELG SOEIAJ−20 (Pb−Free) 2000 Tape & Reel Device MC74HC540ANG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 MC74HC540A MAXIMUM RATINGS Symbol VCC Parameter Value Unit *0.5 to )7.0 V *0.5 to VCC )0.5 V *0.5 v VO v VCC )0.5 V DC Supply Voltage VI DC Input Voltage VO DC Output Voltage (Note 1) IIK DC Input Diode Current $20 mA IOK DC Output Diode Current $35 mA IO DC Output Sink Current $35 mA ICC DC Supply Current per Supply Pin $75 mA IGND DC Ground Current per Ground Pin $75 mA TSTG Storage Temperature Range *65 to )150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias qJA Thermal Resistance PD Power Dissipation in Still Air at 85_C MSL Moisture Sensitivity FR Flammability Rating VESD ILATCHUP _C _C PDIP SOIC TSSOP 67 96 128 _C/W PDIP SOIC TSSOP 750 500 450 mW Level 1 Oxygen Index: 30% − 35% ESD Withstand Voltage Latchup Performance 260 )150 UL 94 V0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) u2000 u200 u1000 V Above VCC and Below GND at 85_C (Note 5) $300 mA Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol VCC Vin, Vout Parameter Min Max Unit DC Supply Voltage (Referenced to GND) 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V *55 )125 _C 0 0 0 1000 500 400 ns TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 3) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level. http://onsemi.com 3 MC74HC540A DC CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Condition VCC V −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V |Iout| ≤ 20 mA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage Vout = VCC − 0.1 V |Iout| ≤ 20 mA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOH Minimum High−Level Output Voltage Vin = VIL |Iout| ≤ 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Vin = VIL VOL Maximum Low−Level Output Voltage |Iout| ≤ 3.6 mA |Iout| ≤ 6.0 mA |Iout| ≤ 7.8 mA Vin = VIH |Iout| ≤ 20 mA Vin = VIH |Iout| ≤ 3.6 mA |Iout| ≤ 6.0 mA |Iout| ≤ 7.8 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA IOZ Maximum Three−State Leakage Current Output in High Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 ±0.5 ±5.0 ±10.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4 40 160 mA AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V −55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 3 and 5) 2.0 3.0 4.5 6.0 80 30 18 15 100 40 23 20 120 55 28 25 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Output Y (Figures 4 and 6) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Output Y (Figures 4 and 6) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 3 and 5) 2.0 3.0 4.5 6.0 60 22 12 10 75 28 15 13 90 34 18 15 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum 3−State Output Capacitance (Output in High Impedance State) 15 15 15 pF Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Per Buffer) (Note 7) 7. Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC . http://onsemi.com 4 35 pF MC74HC540A OE1 or OE2 tf tr VCC 90% 10% tPHL tPLH GND 50% HIGH IMPEDANCE 10% tPZH 50% GND tPLZ OUTPUT Y 90% OUTPUT Y 50% 50% tPZL 50% INPUT A VCC tPHZ 90% 10% Figure 3. Switching Waveform HIGH IMPEDANCE Figure 4. Switching Waveform TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST VOH 50% OUTPUT Y tTLH tTHL VOL OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance 1kW CL * CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH. *Includes all probe and jig capacitance Figure 5. Test Circuit Figure 6. Test Circuit To 7 Other Inverters VCC One of Eight Inverters INPUT A OUTPUT Y OE1 OE2 Figure 7. Logic Detail PIN DESCRIPTIONS INPUTS device functions as an inverter. When a high voltage is applied to either input, the outputs assume the high impedance state. A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9) Data input pins. Data on these pins appear in inverted form on the corresponding Y outputs, when the outputs are enabled. OUTPUTS Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14, 13, 12, 11) CONTROLS Device outputs. Depending upon the state of the output enable pins, these outputs are either inverting outputs or high−impedance outputs. OE1, OE2 (PINS 1, 19) Output enables (active−low). When a low voltage is applied to both of these pins, the outputs are enabled and the http://onsemi.com 5 MC74HC540A PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. −A− 20 11 1 10 B L C −T− K SEATING PLANE M N E G F J D 20 PL 20 PL 0.25 (0.010) 0.25 (0.010) M T A M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 M SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G A 20 11 X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q B M D 18X e A1 SEATING PLANE C T http://onsemi.com 6 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74HC540A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B −U− PIN 1 IDENT 1 SECTION N−N 0.25 (0.010) N 10 M 0.15 (0.006) T U S N A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 7 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC540A PACKAGE DIMENSIONS SOEIAJ−20 F SUFFIX CASE 967−01 ISSUE A 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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