MC74HC573AFELG

MC74HC573A Octal 3-State Noninverting Transparent Latch High−Performance Silicon−Gate CMOS The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The HC573A is identical in function to the HC373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. www.onsemi.com SOIC−20 DW SUFFIX CASE 751D TSSOP−20 DT SUFFIX CASE 948E PIN ASSIGNMENT Features • • • • • • • • OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA In Compliance with the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 218 FETs or 54.5 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 MARKING DIAGRAMS 20 20 LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LATCH ENABLE OUTPUT ENABLE 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 Q0 Q4 SOIC−20 NONINVERTING OUTPUTS Q5 Q6 Q7 1 FUNCTION TABLE PIN 20 = VCC PIN 10 = GND Inputs Output Enable Value Units Internal Gate Count* 54.5 ea. Internal Gate Progation Delay 1.5 ns Internal Gate Power Dissipation 5.0 mW 0.0075 pJ Speed Power Product Output Latch Enable L H L H L L H X X = Don’t Care Z = High Impedance D Q H L X X H L No Change Z ORDERING INFORMATION *Equivalent to a two−input NAND gate. © Semiconductor Components Industries, LLC, 2014 TSSOP−20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) 11 Design Criteria May, 2018 − Rev. 17 1 1 Q2 Q3 HC 573A ALYWG G 74HC573A AWLYYWWG Q1 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LATCH ENABLE See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 1 Publication Order Number: MC74HC573A/D MC74HC573A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature –65 to +150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (TSSOP or SOIC Package) SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/°C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C 0 0 0 1000 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol VIH Parameter Minimum High−Level Input Voltage Test Conditions Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA VIL Maximum Low−Level Input Voltage VOH Minimum High−Level Output Voltage Maximum Low−Level Output Voltage Guaranteed Limit –55 to 25_C v85_C v125_C Unit V 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 18 0.5 0.9 1.35 1.8 V Vin = VIH or VIL |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 Vin = VIH or VIL VOL VCC V |Iout| ≤ 2.4mA |Iout| v 6.0 mA |Iout| v 7.8 mA Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA Vin = VIH or VIL |Iout| ≤ 2.4mA |Iout| v 6.0 mA |Iout| v 7.8 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 ±0.5 ±5.0 ±10 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND IIoutI = 0 mA 6.0 4.0 40 160 mA www.onsemi.com 2 MC74HC573A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol tPLH, tPHL VCC V Parameter Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Guaranteed Limit –55 to 25_C v85_C v125_C 2.0 3.0 4.5 6.0 150 100 30 26 190 140 38 33 225 180 45 38 Unit ns tPLH, tPHL Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) 2.0 3.0 4.5 6.0 160 105 32 27 200 145 40 34 240 190 48 41 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) 2.0 3.0 4.5 6.0 60 27 12 10 75 32 15 13 90 36 18 15 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum 3−State Output Capacitance (Output in High−Impedance State) 15 15 15 pF Typical @ 25°C, VCC = 5.0 V CPD 23 Power Dissipation Capacitance (Per Enabled Output)* pF * Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter Figure VCC V –55 to 25_C Min Max v85_C Min Max v125_C Min Max Unit tsu Minimum Setup Time, Input D to Latch Enable 4 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns th Minimum Hold Time, Latch Enable to Input D 4 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Latch Enable 2 2.0 3.0 4.5 6.0 75 60 15 13 95 80 19 16 110 90 22 19 ns tr, tf Maximum Input Rise and Fall Times 1 2.0 3.0 4.5 6.0 www.onsemi.com 3 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns MC74HC573A SWITCHING WAVEFORMS VCC tr LATCH ENABLE tf VCC 90% 50% 10% INPUT D 50% GND tw GND tPLH tPHL 90% 50% 10% Q tTLH tTHL 50% Q Figure 1. OUTPUT ENABLE Figure 2. VCC 50% VALID GND tPZL Q tPLZ HIGH IMPEDANCE VM tPZH Q tPHZ 10% VOL 90% VOH VM MC74HC573A: VM = VOH x 0.5 MC74HCT573A: VM = 1.3 V @ VCC = 3 V GND tSU HIGH IMPEDANCE Figure 4. D1 OUTPUT DEVICE UNDER TEST D2 CL* D3 *Includes all probe and jig capacitance 2 D4 3 4 5 6 Figure 5. Test Circuit D5 D6 TEST POINT CL* VCC GND TEST POINT 1 kW th 50% LATCH ENABLE D0 OUTPUT VCC 50% INPUT D Figure 3. DEVICE UNDER TEST tPHL tPLH CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. D7 7 8 9 LATCH ENABLE OUTPUT ENABLE D Q LE 19 D Q LE 18 D Q LE 17 D Q LE 16 D Q LE 15 D Q LE 14 D Q LE 13 D Q LE 12 11 1 *Includes all probe and jig capacitance Figure 6. Test Circuit Figure 7. EXPANDED LOGIC DIAGRAM www.onsemi.com 4 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MC74HC573A ORDERING INFORMATION Package Shipping† MC74HC573ADWG SOIC−20 WIDE (Pb−Free) 38 Units / Rail MC74HC573ADWR2G SOIC−20 WIDE (Pb−Free) 1000 Tape & Reel MC74HC573ADTG TSSOP−20 (Pb−Free) 75 Units / Rail MC74HC573ADTR2G TSSOP−20 (Pb−Free) 2500 Tape & Reel NLV74HC573ADTR2G* TSSOP−20 (Pb−Free) 2500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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