MC74HC597ADTG

MC74HC597A 8-Bit Serial or ParallelInput/Serial-Output Shift Register with Input Latch High−Performance Silicon−Gate CMOS The MC74HC597A is identical in pinout to the LS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of an 8−bit input latch which feeds parallel data to an 8−bit shift register. Data can also be loaded serially. The HC597A is similar in function to the HC589A, which is a 3−state device. http://onsemi.com MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 16 1 1 Features • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 516 FETs or 129 Equivalent Gates These are Pb−Free Devices* HC597AG AWLYWW 16 16 1 TSSOP−16 DT SUFFIX CASE 948F HC 597A ALYWG G 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2013 July, 2013 − Rev. 3 1 Publication Order Number: MC74HC597A/D MC74HC597A B 1 16 VCC C 2 15 A D 3 14 E 4 13 F 5 12 SA SERIAL SHIFT/ PARALLEL LOAD LATCH CLOCK G 6 11 SHIFT CLOCK H 7 10 RESET GND 8 9 QH SERIAL DATA INPUT SA A B C PARALLEL DATA INPUTS D E F Figure 1. Pin Assignment G H LATCH CLOCK SHIFT CLOCK SERIAL SHIFT/ PARALLEL LOAD RESET 14 15 1 2 3 4 5 INPUT LATCH SHIFT REGISTER 6 7 9 12 QH SERIAL DATA OUTPUT 11 PIN 16 = VCC PIN 8 = GND 13 10 Figure 2. Logic Diagram ORDERING INFORMATION Package Shipping† MC74HC597ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC597ADR2G SOIC−16 (Pb−Free) 2500 Units / Reel MC74HC597ADTR2G TSSOP−16 (Pb−Free) 2500 Units / Reel MC74HC597ADTG TSSOP−16 (Pb−Free) 96 Units / Tube Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 MC74HC597A MAXIMUM RATINGS* Symbol Parameter Value Unit – 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† TSSOP Package† 750 500 450 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP) _C 260 300 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C — Ceramic DIP: – 10 mW/_C from 100_ to 125_C — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V – 55 + 125 _C 0 0 0 0 1000 600 500 400 ns http://onsemi.com 3 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HC597A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25_C v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 μA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 44 5.9 1.9 44 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Vin = VIH or VIL VOL Maximum Low−Level Output Voltage |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA Vin = VIH or VIL |Iout| v 20 μA Vin = VIH or VIL |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 μA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 μA 6.0 4 40 160 μA http://onsemi.com 4 MC74HC597A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25_C v 85_C v 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle), Shift Clock (Figures 4 and 10) 2.0 3.0 4.5 6.0 10 15 30 50 9 14 28 45 8 12 25 40 MHz tPLH, tPHL Maximum Propagation Delay, Latch Clock to QH (Figures 3 and 10) 2.0 3.0 4.5 6.0 175 100 40 30 225 110 50 40 275 125 60 50 ns tPLH, tPHL Maximum Propagation Delay, Shift Clock to QH (Figures 4 and 10) 2.0 3.0 4.5 6.0 160 90 30 25 200 130 40 30 240 160 48 40 ns tPHL Maximum Propagation Delay, Reset to QH (Figures 5 and 10) 2.0 3.0 4.5 6.0 160 90 30 25 200 130 40 30 240 160 48 40 ns tPLH, tPHL Maximum Propagation Delay, Serial Shift/Parallel Load to QH (Figures 6 and 10) 2.0 3.0 4.5 6.0 160 90 30 25 200 130 40 30 240 160 48 40 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 3 and 10) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns Maximum Input Capacitance — 10 10 10 pF Cin Typical @ 25°C, VCC = 5.0 V CPD 40 Power Dissipation Capacitance (Per Package)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC 2f pF + ICC VCC . PIN DESCRIPTIONS DATA INPUTS Reset (Pin 10) A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7) Asynchronous, Active−low shift register reset. A low level applied to this input resets the shift register to a low level, but does not change the data in the input latch. Parallel data inputs. Data on these inputs is stored in the input latch on the rising edge of the Latch Clock input. Shift Clock (Pin 11) SA (Pin 14) Serial shift register clock. A low−to−high transition on this input shifts data on the Serial Data Input into the shift register and data in stage H is shifted out Q H , being replaced by the data previously stored in stage G. Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input it Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/Parallel Load is low. Latch Clock (Pin 12) CONTROL INPUTS Latch clock. A low−to−high transition on this input loads the parallel data on inputs A−H into the input latch. Serial Shift/Parallel Load (Pin 13) Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the input latch, and serial shifting is inhibited. OUTPUT QH (Pin 9) Serial data output. This pin is the output from the last stage of the shift register. http://onsemi.com 5 MC74HC597A TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25_C v 85_C v 125_C Unit tsu Minimum Setup Time, Parallel Data inputs A−H to Latch Clock (Figure 7) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns tsu Minimum Setup Time, Serial Data Input SA to Shift Clock (Figure 8) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns tsu Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock (Figure 9) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns th Minimum Hold Time, Latch Clock to Parallel Data Inputs A−H (Figure 7) 2.0 3.0 4.5 6.0 15 10 2 2 20 15 3 3 30 25 5 4 ns th Minimum Hold Time, Shift Clock to Serial Data Input SA (Figure 8) 2.0 3.0 4.5 6.0 2 2 2 2 2 2 2 2 2 2 2 2 ns trec Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 5) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns tw Minimum Pulse Width, Latch Clock and Shift Clock (Figures 3 and 4) 2.0 3.0 4.5 6.0 60 35 12 10 70 40 15 13 80 45 19 16 ns tw Minimum Pulse Width, Reset (Figure 5) 2.0 3.0 4.5 6.0 60 35 12 10 70 40 15 13 80 45 19 16 ns tw Minimum Pulse Width, Serial Shift/Parallel Load (Figure 6) 2.0 3.0 4.5 6.0 60 35 12 10 70 40 15 13 80 45 19 16 ns Maximum Input Rise and Fall Times (Figure 3) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns tr, tf NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). http://onsemi.com 6 MC74HC597A FUNCTION TABLE Inputs Shift Clock Parallel Inputs A−H Latch Contents Shift Register Contents Output QH Reset Serial Shift/ Parallel Load Reset shift register L X X X X U L L Reset shift register; load parallel data into data latch L X X X a−h a−h L L Load parallel data into data latch H H L,H, X a−h a−h U U Transfer latch contents to shift register H L L, H, X X X U LRN → SRN LRH Contents of data latch and shift register are unchanged H H L, H, L,H, X X U U U Load parallel data into data latch and shift register H L X X a−h a−h a−h h Shift serial data into shift register H H D X * SRA = D; SRN → SRN + 1 SRG → SRH Load parallel data into data latch and shift serial data into shift register H H D a−h a−h SRA = D; SRN → SRN + 1 SRG → SRH Operation LR = latch register contents SR = shift register contents * = depends on latch clock input Latch Clock Resulting Function Serial Input SA L, H, X a−h = data at parallel data inputs A−H D = data (L, H) at serial data input SA http://onsemi.com 7 U = remains unchanged X = don’t care MC74HC597A SWITCHING WAVEFORMS tw tr LATCH CLOCK 1/fmax tf tw VCC 90% 50% 10% SHIFT CLOCK GND tPLH GND tPLH tPHL 90% 50% 10% QH VCC 50% QH tTLH tPHL 50% tTHL Figure 3. (Serial Shift/Parallel Load = L) tw Figure 4. (Serial Shift/Parallel Load = H) VCC 50% RESET GND tPHL tw SERIAL SHIFT/ PARALLEL LOAD 50% QH trec VCC 50% 50% tPLH tPHL GND QH 50% SHIFT CLOCK Figure 5. Figure 6. VALID PARALLEL DATA A/H VALID VCC SERIAL DATA INPUT SA 50% GND tsu VCC 50% GND th tsu th VCC LATCH CLOCK VCC 50% SHIFT CLOCK 50% GND GND Figure 7. Figure 8. TEST POINT SERIAL SHIFT/ PARALLEL LOAD VCC OUTPUT 50% DEVICE UNDER TEST GND tsu SHIFT CLOCK VCC CL* 50% GND *Includes all probe and jig capacitance Figure 9. Figure 10. Test Circuit http://onsemi.com 8 MC74HC597A EXPANDED LOGIC DIAGRAM SERIAL DATA 14 INPUT, SA SHIFT CLOCK RESET 11 10 SERIAL SHIFT/ 13 PARALLEL LOAD LATCH CLOCK A 12 15 STAGE A D Q C D S C Q R STAGE B B 1 D Q C D S C Q R PARALLEL DATA INPUTS C D E F G 2 STAGE C* 3 STAGE D* 4 STAGE E* 5 STAGE F* 6 STAGE G* STAGE H H 7 D Q C D S C Q R *NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above. Figure 11. Extended Logic Diagram http://onsemi.com 9 9 QH MC74HC597A TIMING DIAGRAM SHIFT CLOCK SERIAL DATA INPUT, SA RESET SERIAL SHIFT PARALLEL LOAD LATCH CLOCK PARALLEL DATA INPUTS A H L L B L L L C H L L D L L L E H L H F H L H G L L L H H H H L QH RESET SHIFT REGISTER L H L H SERIAL SHIFT H L H L H LOAD LATCH Figure 12. Timing Diagram http://onsemi.com 10 H L L SERIAL SHIFT SERIAL SHIFT LOAD LATCH PARALLEL LOAD SHIFT REGISTER L PARALLEL LOAD SHIFT REGISTER L H L H SERIAL SHIFT PARALLEL LOAD LATCH AND SHIFT REGISTER H MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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