MC74HCT04ADT

MC74HCT04A Hex Inverter With LSTTL−Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT04A may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. The HCT04A is identical in pinout to the LS04. • • • • • • • http://onsemi.com MARKING DIAGRAMS Output Drive Capability: 10 LSTTL Loads TTL/NMOS−Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5V Low Input Current: 1µA In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 48 FETs or 12 Equivalent Gates 14 PDIP−14 N SUFFIX CASE 646 MC74HCT04AN AWLYYWW 1 14 SOIC−14 D SUFFIX CASE 751A HCT04A AWLYWW LOGIC DIAGRAM 1 14 A1 A2 A3 1 2 3 4 5 6 9 8 Y2 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week Y3 Y=A A4 A5 A6 11 10 13 12 HCT 04A ALYW TSSOP−14 DT SUFFIX CASE 948G Y1 Pin 14 = VCC Pin 7 = GND Y4 FUNCTION TABLE Inputs Outputs A Y L H H L Y5 Y6 Pinout: 14−Lead Packages (Top View) VCC A6 Y6 A5 Y5 A4 Y4 14 13 12 11 10 9 8 ORDERING INFORMATION Device 1 A1 2 Y1 3 A2 4 Y2  Semiconductor Components Industries, LLC, 2000 March, 2000 − Rev. 7 5 A3 6 Y3 7 GND 326 Package Shipping MC74HCT04AN PDIP−14 2000 / Box MC74HCT04AD SOIC−14 55 / Rail MC74HCT04ADR2 SOIC−14 2500 / Reel MC74HCT04ADT TSSOP−14 96 / Rail MC74HCT04ADTR2 TSSOP−14 2500 / Reel Publication Order Number: MC74HCT04A/D MC74HCT04A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit – 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air 750 500 450 mW Tstg Storage Temperature Range – 65 to + 150
C Iin TL Plastic DIP† SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND  (Vin or Vout)  VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/
C from 65
to 125
C SOIC Package: – 7 mW/
C from 65
to 125
C TSSOP Package: − 6.1 mW/
C from 65
to 125
C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Figure 1) Min Max Unit 4.5 5.5 V 0 VCC V – 55 + 125
C 0 500 ns http://onsemi.com 327 MC74HCT04A DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1V |Iout| ≤ 20µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage Vout = VCC − 0.1V |Iout| ≤ 20µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High−Level Output Voltage Vin = VIL |Iout| ≤ 20µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V 4.5 3.98 3.84 3.70 VOL Maximum Low−Level Output Voltage 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 4.5 0.26 0.33 0.40 |Iout| ≤ 4.0mA Vin = VIL Vin = VIH |Iout| ≤ 20µA |Iout| ≤ 4.0mA Vin = VIH V Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0µA 5.5 1 10 40 µA ∆ICC Additional Quiescent Supply Current Vin = 2.4V, Any One Input Vin GND, Other Inputs i = VCC or GND Iout = 0µA Iin ≥ −55°C 25 to 125°C 2.9 2.4 mA 5.5 1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + Σ∆ICC. AC CHARACTERISTICS (VCC = 5.0V ±10%, CL = 50pF, Input tr = tf = 6ns) Guaranteed Limit Symbol Parameter −55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) 15 17 19 21 22 26 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 15 19 22 ns Cin Maximum Input Capacitance 10 10 10 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V 22 CPD Power Dissipation Capacitance (Per Inverter)* pF * Used to determine the no−load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 328 MC74HCT04A tf INPUT A tr 3.0V 2.7V 1.3V 0.3V GND tPLH tPHL 90% OUTPUT Y 1.3V 10% tTHL tTLH Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 2. Test Circuit A Y Figure 3. Expanded Logic Diagram (1/6 of the Device Shown) http://onsemi.com 329