MC74HCT08A

MC74HCT08A Quad 2-Input AND Gate with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT08A is identical in pinout to the LS08. The device inputs are compatible with Standard CMOS or LSTTL outputs. Features http://onsemi.com MARKING DIAGRAMS 14 PDIP−14 N SUFFIX CASE 646 1 14 14 1 SOIC−14 D SUFFIX CASE 751A 1 A1 B1 A2 B2 A3 B3 A4 B4 1 2 4 5 9 10 12 13 PIN 14 = VCC PIN 7 = GND 3 Y1 14 6 Y2 Y = AB 8 Y3 1 TSSOP−14 DT SUFFIX CASE 948G 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) 14 HCT 08 ALYW G G HCT08AG AWLYWW • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 V to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 24 FETs or 6 Equivalent Gates These are Pb−Free Devices 14 1 MC74HCT08AN AWLYYWWG 11 Y4 FUNCTION TABLE Inputs A B L H L H Output Y L L L H Figure 1. Logic Diagram Pinout: 14−Lead Packages (Top View) VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8 L L H H ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. 1 A1 2 B1 3 Y1 4 A2 5 B2 6 Y2 7 GND Figure 2. Pinout © Semiconductor Components Industries, LLC, 2009 November, 2009 − Rev. 8 1 Publication Order Number: MC74HCT08A/D MC74HCT08A MAXIMUM RATINGS Symbol VCC Vin Vout Iin Iout ICC PD Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP† SOIC Package† TSSOP Package† Value −0.5 to +7.0 −0.5 to VCC +0.5 −0.5 to VCC +0.5 ±20 ±25 ±50 750 500 450 −65 to +150 260 Unit V V V mA mA mA mW This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating − Plastic DIP: − 10 mW/°C from 65°C to 125°C SOIC Package: − 7 mW/°C from 65°C to 125°C TSSOP Package: − 6.1 mW/°C from 65°C to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout TA tr, tf DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 3) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Parameter Min 2.0 0 −55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns http://onsemi.com 2 MC74HCT08A DC CHARACTERISTICS (Voltages Referenced to GND) Symbol VIH VIL VOH Parameter Minimum High−Level Input Voltage Maximum Low−Level Input Voltage Minimum High−Level Output Voltage Condition Vout = 0.1 V or VCC −0.1 V |Iout| ≤ 20 mA Vout = 0.1 V or VCC − 0.1 V |Iout| ≤ 20 mA Vin = VIH or VIL |Iout| ≤ 20 mA Vin =VIH or VIL VOL Maximum Low−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20mA Vin = VIH or VIL Iin ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND Iout = 0 mA |Iout| ≤ 4.0 mA |Iout| ≤ 4.0 mA VCC V 4.5 to 5.5 4.5 to 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 Guaranteed Limit −55 to 25°C 2.0 0.8 4.4 5.4 3.98 0.1 0.1 0.26 ±0.1 1.0 ≤85°C 2.0 0.8 4.4 5.4 3.84 0.1 0.1 0.33 ±1.0 10 ≤125°C 2.0 0.8 4.4 5.4 3.70 0.1 0.1 0.40 ±1.0 40 mA mA V Unit V V V AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%) Symbol tPLH, tPHL tTLH, tTHL Cin Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 3 and 4) Maximum Output Transition Time, Any Output (Figures 3 and 4) Maximum Input Capacitance tPLH tPHL VCC V 5.0 5.0 Guaranteed Limit −55 to 25°C 15 17 15 10 ≤85°C 19 21 19 10 ≤125°C 22 26 22 10 Unit ns ns pF Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Per Buffer)* 2f 20 + ICC VCC . pF *Used to determine the no−load dynamic power consumption: PD = CPD VCC ORDERING INFORMATION Device MC74HCT08ANG MC74HCT08ADG MC74HCT08ADR2G MC74HCT08ADTR2G MC74HCT08AFELG Package PDIP−14 (Pb−Free) SOIC−14 (Pb−Free) SOIC−14 (Pb−Free) TSSOP−14* SOEIAJ−14 (Pb−Free) 2000/Tape & Reel Shipping† 25 Units / Rail 55 Units / Rail 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 3 MC74HCT08A tr INPUT A OR B (VI) VI = GND to 3.0 V Vm = 1.3 V OUTPUT Y tPLH 90% Vm 10% tTLH tTHL 90% Vm 10% tPHL tf VCC GND Figure 3. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 4. Test Circuit A B Y Figure 5. Expanded Logic Diagram (1/4 of the Device) http://onsemi.com 4 MC74HCT08A PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01 A F N −T− SEATING PLANE L C H G D 14 PL K M J M DIM A B C D F G H J K L M N 0.13 (0.005) http://onsemi.com 5 MC74HCT08A PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B M 14X K REF 0.10 (0.004) 0.15 (0.006) T U S TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B −U− N F DETAIL E K K1 J J1 0.15 (0.006) T U S SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.36 14X 14X 1.26 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.65 PITCH DIMENSIONS: MILLIMETERS MC74HCT08A PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE J −A− 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −B− P 7 PL 0.25 (0.010) M B M 1 7 G C −T− SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) M K TB S M A S J SOLDERING FOOTPRINT* 7X DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 7 MC74HCT08A/D