MC74HCT14ADR2G

MC74HCT14A Hex Schmitt-Trigger Inverter with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS http://onsemi.com The MC74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high−speed CMOS inputs. The HCT14A is useful to “square up” slow input rise and fall times. Due to the hysteresis voltage of the Schmitt trigger, the HCT14A finds applications in noisy environments. SOIC−14 NB D SUFFIX CASE 751A Features • • • • • • • • • Output Drive Capability: 10 LSTTL Loads TTL/NMOS−Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA In Compliance With the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 72 FETs or 18 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free and are RoHS Compliant TSSOP−14 DT SUFFIX CASE 948G PIN ASSIGNMENT A1 1 14 VCC Y1 2 13 A6 A2 3 12 Y6 Y2 4 11 A5 A3 5 10 Y5 Y3 6 9 A4 GND 7 8 Y4 MARKING DIAGRAMS LOGIC DIAGRAM A1 1 2 3 4 14 14 HCT 14A ALYWG G HCT14AG AWLYWW Y1 1 A2 A3 A4 5 6 9 8 11 10 1 SOIC−14 NB Y2 A L, WL Y, YY W, WW G or G Y3 TSSOP−14 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Y4 FUNCTION TABLE A5 A6 13 Y=A 12 Y6 PIN 14 = VCC PIN 7 = GND © Semiconductor Components Industries, LLC, 2014 October, 2014 − Rev. 14 Y5 Input A Output Y L H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. 1 Publication Order Number: MC74HCT14A/D MC74HCT14A MAXIMUM RATINGS Symbol VCC Parameter Value Unit DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V VI DC Input Voltage (Referenced to GND) −0.5 to VCC + 0.5 V VO DC Output Voltage (Referenced to GND) −0.5 to VCC + 0.5 V IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±25 mA IO DC Output Sink Current ±25 mA ICC DC Supply Current per Supply Pin ±50 mA IGND DC Ground Current per Ground Pin ±50 mA TSTG Storage Temperature Range −65 to +150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction Temperature under Bias +150 _C qJA Thermal Resistance SOIC TSSOP 125 170 _C/W PD Power Dissipation in Still Air at 85_C SOIC TSSOP 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup Level 1 Oxygen Index: 30% − 35% ESD Withstand Voltage Latchup Performance UL 94 V−0 @ 0.125 in Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 85_C (Note 4) > 4000 > 300 > 1000 V ±300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to JESD22−C101−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI, VO Parameter Min Max Unit DC Supply Voltage (Referenced to GND) 4.5 5.5 V DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V −55 +125 _C − (Note 5) ns TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. No Limit when VI [ 50% VCC, ICC > 1 mA. 6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. http://onsemi.com 2 MC74HCT14A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Temperature Limit VCC Min Max Min v125_C Parameter VT)max Maximum Positive−Going Input Threshold Voltage VO = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 VT)min Minimum Positive−Going Input Threshold Voltage VO = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 VT*max Maximum Negative−Going Input Threshold Voltage VO = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 VT*min Minimum Negative−Going Input Threshold Voltage VO = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 VH max Maximum Hysteresis Voltage VO = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 VH min Minimum Hysteresis Voltage VO = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 0.4 0.4 0.4 0.4 0.4 04 VOH Minimum High−Level Output Voltage VI < VT*min |Iout| ≤ 20 mA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 VI < VT*min |Iout| ≤ 4.0 mA 4.5 3.98 3.84 3.7 VI ≥ VT)max |Iout| ≤ 20 mA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 VI ≥ VT)max |Iout| ≤ 4.0 mA 4.5 0.26 0.33 0.4 Maximum Low−Level Output Voltage Volts v85_C Symbol VOL Test Conditions *55_C to 25_C 1.9 2.1 1.2 1.4 Max 1.9 2.1 1.2 1.4 1.2 1.4 0.5 0.6 Min Unit 1.9 2.1 V 1.2 1.4 1.2 1.4 0.5 0.6 1.4 1.5 Max V 1.2 1.4 0.5 0.6 1.4 1.5 1.4 1.5 V V IIK Maximum Input Leakage Current VI = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per package) VI = VCC or GND Iout = 0 mA 5.5 1.0 10 40 mA DICC Additional Quiescent Supply Current VI = 2.4 V, Any One Input VI = VCC or GND, Other Inputs lout = 0 mA w*55_C 25_C to 125_C 2.9 2.4 5.5 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns) Guaranteed Limit *55_C to 25_C Symbol Parameter Test Conditions Figures Min Max tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (L to H) VCC = 5.0 V ±10% CL = 50 pF, Input tr = tf = 6.0 ns 1&2 32 tTLH, tTHL Maximum Output Transition Time, Any Output VCC = 5.0 V ±10% CL = 50 pF, Input tr = tf = 6.0 ns 1&2 15 v85_C Min Max v125_C Min Max Unit 40 48 ns 19 22 ns Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance, per Inverter (Note 7) 32 7. Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . http://onsemi.com 3 pF MC74HCT14A tr tf INPUT A 2.7 V 1.3 V 0.3 V OUTPUT Y 3V GND tPLH tPHL 90% 1.3 V 10% tTLH tTHL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance. Figure 2. Test Circuit ORDERING INFORMATION Device MC74HCT14ADG NLV74HCT14ADG* MC74HCT14ADR2G NLV74HCT14ADR2G* MC74HCT14ADTR2G NLV74HCT14ADTR2G* Package Shipping† SOIC−14 NB (Pb−Free) 55 Units / Rail SOIC−14 NB (Pb−Free) 2500 / Tape & Reel TSSOP−14 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G ISSUE C 14 DATE 17 FEB 2016 1 SCALE 2:1 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− K1 J J1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX ALYWG G 7.06 1 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: 98ASH70246A DESCRIPTION: TSSOP−14 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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