MC74HCT241A

MC74HCT241A Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver with LSTTL-Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT241A is identical in pinout to the LS241. This device may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. The HCT241A is an octal noninverting buffer/line driver/line receiver designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. The device has non−inverted outputs and two output enables. Enable A is active−low and Enable B is active−high. The HCT241A is similar in function to the HCT244. See also HCT240. Features http://onsemi.com PDIP−20 N SUFFIX CASE 738 1 1 SOIC−20W DW SUFFIX CASE 751D • • • • • • • • Output Drive Capability: 15 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 118 FETs or 29.5 Equivalent Gates Pb−Free Packages are Available* TSSOP−20 DT SUFFIX CASE 948E 1 ORDERING INFORMATION See detailed ordering, shipping information, and marking information in the package dimensions section on page 6 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 8 1 Publication Order Number: MC74HCT241A/D MC74HCT241A LOGIC DIAGRAM A1 A2 A3 A4 DATA INPUTS B1 B2 B3 B4 11 13 15 17 9 7 5 3 YB1 YB2 YB3 YB4 2 4 6 8 18 16 14 12 YA1 YA2 YA3 YA4 NONINVERTING OUTPUTS PIN ASSIGNMENT ENABLE A A1 YB4 A2 YB3 A3 YB2 A4 YB1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC ENABLE B YA1 B4 YA2 B3 YA3 B2 YA4 B1 FUNCTION TABLE Inputs Enable A L L H Inputs Enable B H H L B L H X A L H X Output YA L H Z Output YB L H Z 1 OUTPUT ENABLE A ENABLES ENABLE B 19 PIN 20 = VCC PIN 10 = GND Z = high impedance X = don’t care http://onsemi.com 2 MC74HCT241A MAXIMUM RATINGS* Symbol VCC Vin Vout Iin Iout ICC PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) Value – 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5 ± 20 ± 35 ± 75 750 500 – 65 to + 150 260 300 Unit V V V mA mA mA mW _C _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î Î ÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î VCC TA DC Supply Voltage (Referenced to GND) 4.5 0 0 5.5 V V Vin, Vout tr, tf DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC 500 – 55 + 125 _C ns Symbol Parameter Min Max Unit DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit – 55 to 25_C 2 2 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 ± 0.1 ± 0.5 v 85_C 2 2 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 ± 1.0 ± 5.0 v 125_C 2 2 08 0.8 4.4 5.4 3.7 0.1 0.1 0.4 ± 1.0 ± 10 μA μA V Unit V V V Symbol VIH VIL VOH Parameter Minimum High−Level Input Voltage Maximum Low−Level Input Voltage Minimum High−Level Output Voltage Test Conditions Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA Vin = VIH or VIL |Iout| v 20 μA Vin = VIH or VIL |Iout| v 6 mA VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 VOL Maximum Low−Level Output Voltage Vin = VIH or VIL |Iout| v 20 μA Vin = VIH or VIL |Iout| v 6 mA Iin IOZ Maximum Input Leakage Current Maximum Three−State Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current Vin = VCC or GND Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 μA Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 μA ICC ΔICC 5.5 4 ≥ −55_C 40 160 25_C to 125_C 2.4 μA 5.5 2.9 mA 1. Total Supply Current = ICC + ΣΔICC. http://onsemi.com 3 MC74HCT241A AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL Cin Cout Parameter Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance Maximum Three−State Output Capacitance (Output in High−Impedance State) – 55 to 25_C 23 30 26 12 10 15 v 85_C 29 38 33 15 10 15 v 125_C 35 45 39 18 10 15 Unit ns ns ns ns pF pF Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 55 pF * Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC . SWITCHING WAVEFORMS 3V ENABLE A 1.3 V GND 3V tr INPUT A OR B tPLH OUTPUT YA OR YB tTLH 90% 1.3 V 10% tTHL OUTPUT Y 2.7 V 1.3 V 0.3 V tPHL tf 3V tPZL GND OUTPUT Y 1.3 V 10% tPZH 1.3 V tPHZ 90% tPLZ ENABLE B 1.3 V GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE Figure 1. Figure 2. TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 kΩ CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL* CL* *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit http://onsemi.com 4 MC74HCT241A LOGIC DETAIL TO THREE OTHER “A” BUFFERS TO THREE OTHER “B” BUFFERS TWO OF 8 BUFFERS INPUT A VCC YA INPUT B VCC YB ENABLE A OUTPUT ENABLES ENABLE B http://onsemi.com 5 MC74HCT241A ORDERING INFORMATION Device MC74HCT241ANG MC74HCT241ADWG MC74HCT241ADWR2G MC74HCT241ADTG MC74HCT241ADTR2G Package PDIP−20 (Pb−Free) SOIC−20 (Pb−Free) SOIC−20 (Pb−Free) TSSOP−20* TSSOP−20* Shipping† 18 Units / Rail 38 Units / Rail 1000 / Tape & Reel 75 Units / Rail 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb−Free. MARKING DIAGRAMS PDIP−20 20 20 MC74HCT241AN AWLYYWWG 1 1 SOIC−20W 20 HCT241A AWLYYWWG 1 TSSOP−20 HCT 241A ALYWG G A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) http://onsemi.com 6 MC74HCT241A PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE E −A− 20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 B 1 10 C L −T− SEATING PLANE K E G F D 20 PL N J 0.25 (0.010) M 20 PL M 0.25 (0.010) TA M M TB M DIM A B C D E F G J K L M N SOIC−20W DW SUFFIX CASE 751D−05 ISSUE G D A 11 X 45 _ q H M B M 20 10X 0.25 E NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 1 10 20X B 0.25 M B TA S B S A e SEATING PLANE h 18X A1 T C http://onsemi.com 7 L MC74HCT241A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 20X K REF M 2X L/2 20 11 J J1 B −U− N L PIN 1 IDENT 1 10 0.15 (0.006) T U S A −V− N F DETAIL E C D 0.100 (0.004) −T− SEATING PLANE G H DETAIL E SOLDERING FOOTPRINT 7.06 1 0.36 16X 16X 1.26 http://onsemi.com 8 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ SECTION N−N 0.25 (0.010) M 0.15 (0.006) T U S 0.10 (0.004) TU S V S K K1 −W− 0.65 PITCH DIMENSIONS: MILLIMETERS MC74HCT241A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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