MC74HCT373AN

ÎÎ ÎÎ MC74HCT373A Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs High−Performance Silicon−Gate CMOS http://onsemi.com The MC74HCT373A may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. The HCT373A is identical in pinout to the LS373. The eight latches of the HCT373A are transparent D−type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched. The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high−impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT373A is identical in function to the HCT573A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT533A, which has inverting outputs. SOIC−20 DW SUFFIX CASE 751D PIN ASSIGNMENT OUTPUT ENABLE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND Features • • • • • • • • Output Drive Capability: 15 LSTTL Loads TTL/NMOS−Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 196 FETs or 49 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant 1 2 3 4 5 6 7 8 9 10 D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LATCH ENABLE OUTPUT ENABLE 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 11 1 © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 13 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LATCH ENABLE 20 20 HCT 373A ALYWG G HCT373A AWLYYWWG 1 1 TSSOP−20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) Q0 Q1 Q2 Q3 20 19 18 17 16 15 14 13 12 11 MARKING DIAGRAMS SOIC−20 LOGIC DIAGRAM TSSOP−20 DT SUFFIX CASE 948E ORDERING INFORMATION Device Package Shipping† MC74HCT373ADWG SOIC−20 (Pb−Free) 38 / Rail MC74HCT373ADWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel Q7 MC74HCT373ADTR2G TSSOP−20 2500 / (Pb−Free) Tape & Reel PIN 20 = VCC PIN 10 = GND †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Q4 NONINVERTING OUTPUTS Q5 Q6 1 Publication Order Number: MC74HCT373A/D MC74HCT373A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Design Criteria Value Units Internal Gate Count* 49 ea. Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 mW 0.0075 pJ Speed Power Product FUNCTION TABLE Inputs Output Output Enable Latch Enable D Q L L L H H H L X H L X X H L No Change Z X = don’t care Z = high impedance *Equivalent to a two−input NAND gate. MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature –65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (SOIC or TSSOP Package) SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. °C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/°C from 65° to 125°C TSSOP Package: −6.1 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) Max Unit 4.5 5.5 V 0 VCC V –55 +125 °C 0 500 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 2 MC74HCT373A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V −55 to 25°C ≤ 85°C ≤ 125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| ≤ 20 mA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20 mA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V Vin = VIH or VIL |Iout| ≤ 6.0 mA 4.5 3.98 3.84 3.7 Vin = VIH or VIL |Iout| ≤ 20 mA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| ≤ 6.0 mA 4.5 0.26 0.33 0.4 VOL Maximum Low−Level Output Voltage V Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 mA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 5.5 ±0.5 ±5.0 ±10 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 5.5 4.0 40 160 mA DICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 mA 5.5 ≥ −55°C 25°C to 125°C 2.9 2.4 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ mA NOTE: 1. Total Supply Current = ICC + SDICC. AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit −55 to 25°C ≤ 85°C ≤ 125°C Unit tPLH, tPHL Maximum Propagation Delay, Input D to Q (Figures 1 and 5) 28 35 42 ns tPLH, tPHL Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) 32 40 48 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 30 38 45 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 35 44 53 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) 12 15 18 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum Three−State Output Capacitance (Output in High−Impedance State) 15 15 15 pF Symbol Parameter Typical @ 25°C, VCC = 5.0 V CPD 65 Power Dissipation Capacitance (Per Latch)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC http://onsemi.com 3 2f + ICC VCC . pF MC74HCT373A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (VCC = 5.0 V ±10%, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter −55 to 25°C ≤ 85°C ≤ 125°C Unit tsu Minimum Setup Time, Input D to Latch Enable (Figure 4) 10 13 15 ns th Minimum Hold Time, Latch Enable to Input D (Figure 4) 10 13 15 ns tw Minimum Pulse Width, Latch Enable (Figure 2) 12 15 18 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 500 500 500 ns EXPANDED LOGIC DIAGRAM D0 3 D1 4 D Q D2 7 D LE Q D3 8 D LE Q D4 13 D LE Q D5 14 D LE Q D6 17 D LE Q D7 18 D LE Q D LE Q LE LATCH 11 ENABLE OUTPUT 1 ENABLE 2 Q0 5 Q1 6 Q2 9 Q3 http://onsemi.com 4 12 Q4 15 Q5 16 Q6 19 Q7 MC74HCT373A SWITCHING WAVEFORMS tr tf INPUT D tw 3V 2.7 V 1.3 V 0.3 V LATCH ENABLE 1.3 V GND tPLH GND tPHL Q 1.3 V tTHL tTLH Figure 1. OUTPUT ENABLE 3V GND tPLZ VALID 3V HIGH IMPEDANCE 1.3 V tPZH Q Figure 2. 1.3 V tPZL Q tPHL tPLH 90% 1.3 V 10% Q 3V 1.3 V 10% VOL 90% VOH INPUT D GND tsu tPHZ 1.3 V 1.3 V th 3V LATCH ENABLE 1.3 V GND HIGH IMPEDANCE Figure 3. Figure 4. TEST CIRCUITS TEST POINT TEST POINT OUTPUT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST CL* 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 5. Figure 6. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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