MC74HCT374AFEL

MC74HCT374A Octal 3−State Noninverting D Flip−Flop with LSTTL−Compatible Inputs High−Performance Silicon−Gate CMOS http://onsemi.com The MC74HCT374A may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. The HCT374A is identical in pinout to the LS374. Data meeting the setup and hold time is clocked to the outputs with the rising edge of Clock. The Output Enable does not affect the state of the flip−flops, but when Output Enable is high, the outputs are forced to the high−impedance state. Thus, data may be stored even when the outputs are not enabled. The HCT374A is identical in function to the HCT574A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT534A, which has inverting outputs. MARKING DIAGRAMS PDIP−20 N SUFFIX CASE 738 20 1 • MC74HCT374AN AWLYYWWG 1 20 SOICW−20 DW SUFFIX CASE 751D 20 HCT374A AWLYYWWG 1 Features • • • • • • • • 20 Output Drive Capability: 15 LSTTL Loads TTL/NMOS−Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA In Compliance With the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 276 FETs or 69 Equivalent Gates Improvements over HCT374 — Improved Propagation Delays — 50% Lower Quiescent Power — Improved Input Noise and Latchup Immunity Pb−Free Packages are Available* 1 20 20 1 TSSOP−20 DT SUFFIX CASE 948E HCT 374A ALYWG G 1 20 SOEIAJ−20 F SUFFIX CASE 967 20 1 74HCT374A AWLYYWWG 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 June, 2005 − Rev. 10 1 Publication Order Number: MC74HCT374A/D MC74HCT374A PIN ASSIGNMENT OUTPUT ENABLE Q0 LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK OUTPUT ENABLE 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 20 VCC 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q0 Q1 5 16 Q6 Q1 Q2 6 15 Q5 Q2 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 10 11 CLOCK Q3 NONINVERTING OUTPUTS Q4 Q5 GND Q6 Q7 FUNCTION TABLE 11 1 1 Inputs Output Enable PIN 20 = VCC PIN 10 = GND L L L H ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ Value Units Internal Gate Count* Design Criteria 69 ea. Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 mW .0075 pJ Speed Power Product Output Clock D Q L,H, X H L X X H L No Change Z X = don’t care Z = high impedance *Equivalent to a two−input NAND gate. ORDERING INFORMATION Package Shipping † MC74HCT374AN PDIP−20 1440 Units / Box MC74HCT374ANG PDIP−20 (Pb−Free) 1440 Units / Box MC74HCT374ADW SOIC−20 38 Units / Rail MC74HCT374ADWG SOIC−20 (Pb−Free) 38 Units / Rail MC74HCT374ADWR2 SOIC−20 1000 Units / Reel MC74HCT374ADWR2G SOIC−20 (Pb−Free) 1000 Units / Reel MC74HCT374ADTR2 TSSOP−20* 2500 Units / Reel MC74HCT374ADTR2G TSSOP−20* 2500 Units / Reel MC74HCT374AFEL SOEIAJ−20 2000 Units / Reel MC74HCT374AFELG SOEIAJ−20 (Pb−Free) 2000 Units / Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 MC74HCT374A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 V V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package) Plastic DIP† SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 4.5 5.5 V DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) 0 VCC V – 55 + 125 _C 0 500 ns ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC V – 55 to 25_C v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V Vin = VIH or VIL |Iout| v 6.0 mA 4.5 3.98 3.84 3.7 Vin = VIH or VIL |Iout| v 20 mA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| v 6.0 mA Symbol VOL Parameter Maximum Low−Level Output Voltage Test Conditions V 4.5 0.26 0.33 0.4 Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 mA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 5.5 ± 0.5 ± 5.0 ± 10 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 5.5 4.0 40 160 mA DICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 mA ≥ −55_C 25_C to 125_C 2.9 2.4 5.5 mA 1. Total Supply Current = ICC + ΣDICC. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D) http://onsemi.com 3 MC74HCT374A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎ Î ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter – 55 to 25_C v 85_C v 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 30 24 20 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 31 39 47 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) 30 38 45 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) 30 38 45 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 12 15 18 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum Three−State Output Capacitance (Output in High−Impedance State) 15 15 15 pF For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D) Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Flip−Flop)* 65 pF * Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎ Î ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter – 55 to 25_C v 85_C v 125_C Unit tsu Minimum Setup Time, Data to Clock (Figure 3) 12 15 18 ns th Minimum Hold Time, Clock to Data (Figure 3) 5.0 5.0 5.0 ns tw Minimum Pulse Width, Clock (Figure 1) 12 15 18 ns Maximum Input Rise and Fall Times (Figure 1) 500 500 500 ns tr, tf http://onsemi.com 4 MC74HCT374A SWITCHING WAVEFORMS tr CLOCK tf GND tPLZ tPZL Q HIGH IMPEDANCE 1.3 V tPHL tPLH 90% 1.3 V 10% 1.3 V GND 1/fmax Q 3V OUTPUT ENABLE VCC 2.7 V 1.3 V 0.3 V tw tPZH Q 10% VOL 90% VOH tPHZ 1.3 V HIGH IMPEDANCE tTHL tTLH Figure 1. Figure 2. VALID DATA 3V 1.3 V tsu GND th 3V CLOCK 1.3 V GND Figure 3. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST C L* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL CONNECT TO GND WHEN TESTING tPHZ AND tPZH 1 kW OUTPUT C L* *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 4. Figure 5. EXPANDED LOGIC DIAGRAM D0 3 D1 4 D Q D C CLOCK D2 7 Q D3 8 D C Q D4 13 D C Q D5 14 D C Q D6 17 D C Q D7 18 D C Q D C Q C 11 OUTPUT 1 ENABLE 2 Q0 5 Q1 6 Q2 9 Q3 http://onsemi.com 5 12 Q4 15 Q5 16 Q6 19 Q7 MC74HCT374A PACKAGE DIMENSIONS PDIP−20 N SUFFIX CASE 738−03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. −A− 20 11 1 10 B C −T− K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 M SOICW−20 DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 18X e A1 SEATING PLANE C T http://onsemi.com 6 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74HCT374A TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE B 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 J J1 B −U− L PIN 1 IDENT SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING PLANE http://onsemi.com 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HCT374A PACKAGE DIMENSIONS SOEIAJ−20 M SUFFIX CASE 967−01 ISSUE O 20 LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D VIEW P e A c DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.81 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 0_ 10 _ 0.028 0.035 −−− 0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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