MC74HCT574A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
http://onsemi.com
The MC74HCT574A is identical in pinout to the LS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states
of the flip−flops, but when Output Enable is high, all device outputs
are forced to the high−impedance state. Thus, data may be stored even
when the outputs are not enabled.
The HCT574A is identical in function to the HCT374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
SOIC−20
DW SUFFIX
CASE 751D
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
D1
D2
D3
D4
D5
D6
D7
GND
Features
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
20
20
HCT
574A
ALYWG
G
HCT574A
AWLYYWWG
1
TSSOP−20
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
Q2
NONINVERTING
OUTPUTS
Q5
Q6
Q7
FUNCTION TABLE
11
1
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
MARKING DIAGRAMS
SOIC−20
Q1
Q4
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
1
Q0
Q3
TSSOP−20
DT SUFFIX
CASE 948E
Inputs
PIN 20 = VCC
PIN 10 = GND
OE
L
L
L
H
Figure 1. Logic Diagram
Output
Clock
D
Q
L,H,
X
H
L
X
X
H
L
No Change
Z
X = don’t care
Z = high impedance
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 11
1
Publication Order Number:
MC74HCT574A/D
MC74HCT574A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Design Criteria
Value
Units
Internal Gate Count*
71.5
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
0.0075
pJ
Speed Power Product
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
–0.5 to +7.0
V
Vin
DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
500
mW
–65 to +150
_C
PD
Power Dissipation in Still Air,
Tstg
Storage Temperature
SOIC Package†
TL
Lead Temperature, 1 mm from Case for 10 secs
(SOIC Package)
_C
260
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: – 7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 2)
Max
Unit
4.5
5.5
V
0
VCC
V
–55
+125
_C
0
500
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
http://onsemi.com
2
MC74HCT574A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
–55 to
25_C
≤ 85_C
≤ 125_C
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
Symbol
VIH
Parameter
Minimum High−Level Input Voltage
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 mA
VIL
Maximum Low−Level Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
VOH
Minimum High−Level Output Voltage
Vin = VIH or VIL
|Iout| ≤ 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
Vin = VIH or VIL
|Iout| ≤ 6.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout| ≤ 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| ≤ 6.0 mA
4.5
0.26
0.33
0.4
VOL
Maximum Low−Level Output Voltage
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
Maximum Quiescent Supply Current
(per Package)
Vin = VCC or GND
Iout = 0 mA
5.5
4.0
40
160
Maximum Three−State Leakage
Current
Vin = VIL or VIH (Note 1)
Vout = VCC or GND
5.5
−0.5
–5.0
–10
Additional Quiescent Supply Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 mA
DICC
V
V
ICC
IOZ
Unit
V
mA
mA
mA
≥ –55_C
25_C to 125_C
2.9
2.4
5.5
mA
1. Output in high−impedance state.
ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
– 55 to
25_C
v 85_C
v 125_C
Unit
fMAX
Maximum Clock Frequency (50% Duty Cycle) (Figures 2 and 5)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 2 and 5)
30
38
45
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28
35
42
ns
tPZH,
tPZL
Maximum Propagation Delay Time, Output Enable to Q
(Figures 3 and 6)
28
35
42
ns
tTLH,
Maximum Output Transition Time, Any Output
(Figures 2, 3 and 5)
12
15
18
ns
Maximum Input Capacitance
10
10
10
pF
tTHL
Cin
Typical @ 25°C, VCC = 5.0 V
CPD
58
Power Dissipation Capacitance (Per Flip−Flop)*
pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
* Used to determine the no−load dynamic power consumption: P D = CPD VCC
2f
+ ICC VCC .
TIMING REQUIREMENTS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25_C
Symbol
Parameter
Figure
Min
Max
v 85_C
Min
Max
v 125_C
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
4
10
13
15
ns
th
Minimum Hold Time, Clock to Data
4
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
2
15
Maximum Input Rise and Fall Times
2
tr, If
19
500
http://onsemi.com
3
22
500
ns
500
ns
MC74HCT574A
EXPANDED LOGIC DIAGRAM
D1
3
D0
2
CLOCK
D3
5
D4
6
D5
7
D6
8
D7
9
11
D
C
C
D
C
Q
Q
ENABLE
OUTPUT
D2
4
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
Q
1
18
19
17
Q1
Q0
16
Q2
15
Q3
14
Q4
13
Q5
12
Q6
Q7
SWITCHING WAVEFORMS
tf
tr
CLOCK
3.0 V
2.7 V
1.3 V
0.3 V
tw
3.0 V
OUTPUT
ENABLE
GND
GND
tPZL
1/fmax
tPHL
tPLH
Q
1.3 V
Q
90%
1.3 V
10%
tTLH
HIGH
IMPEDANCE
1.3 V
tPZH
Q
tPLZ
tPHZ
10%
VOL
90%
VOH
1.3 V
HIGH
IMPEDANCE
tTHL
Figure 2.
Figure 3.
TEST POINT
OUTPUT
VALID
DEVICE
UNDER
TEST
3.0 V
1.3 V
DATA
GND
tsu
CL*
th
3.0 V
1.3 V
GND
CLOCK
*Includes all probe and jig capacitance
Figure 4.
Figure 5. Test Circuit
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
CL*
*Includes all probe and jig capacitance
Figure 6. Test Circuit
http://onsemi.com
4
MC74HCT574A
ORDERING INFORMATION
Package
Shipping†
MC74HCT574ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HCT574ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
MC74HCT574ADTR2G
TSSOP−20
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
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