MC74HCU04ADG

MC74HCU04A Hex Unbuffered Inverter High−Performance Silicon−Gate CMOS The MC74HCU04A is identical in pinout to the LS04 and the MC14069UB. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of six single−stage inverters. These inverters are well suited for use as oscillators, pulse shapers, and in many other applications requiring a high−input impedance amplifier. For digital applications, the HC04A is recommended. http://onsemi.com SOIC−14 NB D SUFFIX CASE 751A TSSOP−14 DT SUFFIX CASE 948G Features PIN ASSIGNMENT • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6.0 V in Oscillator • • • • • • Configurations Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 12 FETs or 3 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free and are RoHS Compliant A1 1 14 VCC Y1 2 13 A6 A2 3 12 Y6 Y2 4 11 A5 A3 5 10 Y5 Y3 6 9 A4 GND 7 8 Y4 MARKING DIAGRAMS 14 14 A1 A2 A3 A4 A5 A6 1 3 2 4 5 6 9 8 11 10 13 Y=A 12 HCU 04A ALYWG G HCU04AG AWLYWW LOGIC DIAGRAM Y1 1 1 TSSOP−14 SOIC−14 NB Y2 A L, WL Y, YY W, WW G or G Y3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Y4 FUNCTION TABLE Y5 Y6 PIN 14 = VCC PIN 7 = GND Inputs A Outputs Y L H H L ORDERING INFORMATION See detailed ordering and shipping information on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 8 1 Publication Order Number: MC74HCU04A/D MC74HCU04A MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 V DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air 500 450 mW Tstg Storage Temperature –65 to +150 _C TL Lead Temperature, 1 mm from case for 10 Seconds SOIC or TSSOP Package SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C − No Limit ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V –55 to 25_C ≤ 85_C ≤ 125_C Unit VIH Minimum High−Level Input Voltage 2.0 3.0 4.5 6.0 1.7 2.5 3.6 4.8 1.7 2.5 3.6 4.8 l.7 2.5 3.6 4.8 V VIL Maximum Low−Level Input Voltage 2.0 3.0 4.5 6.0 0.3 0.5 0.8 1.1 0.3 0.5 0.8 1.1 0.3 0.5 0.8 1.1 V VOH Minimum High−Level Output Voltage 2.0 4.5 6.0 1.8 4.0 5.5 1.8 4.0 5.5 1.8 4.0 5.5 V 3.0 4.5 6.0 2.36 3.86 5.36 2.26 3.76 5.26 2.20 3.70 5.20 Vin = GND |Iout| ≤ 20 mA Vin = GND |Iout| ≤ 2.4 mA |Iout| ≤ 4.0 mA |Iout| ≤ 5.2 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. For VCC = 2.0 V, Vout = 0.2 V or VCC − 0.2 V. http://onsemi.com 2 MC74HCU04A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (continued) Guaranteed Limit Parameter Symbol VOL Test Conditions Maximum Low−Level Output Voltage Vin = VCC |Iout| v 20 mA |Iout| ≤ 2.4 mA |Iout| ≤ 4.0 mA |Iout| ≤ 5.2 mA Vin = VCC VCC V –55 to 25_C ≤ 85_C ≤ 125_C Unit 2.0 4.5 6.0 0.2 0.5 0.5 0.2 0.5 0.5 0.2 0.5 0.5 V 3.0 4.5 6.0 0.32 0.32 0.32 0.32 0.37 0.37 0.32 0.40 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 1 10 40 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. For VCC = 2.0 V, Vout = 0.2 V or VCC − 0.2 V. AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V –55 to 25_C ≤ 85_C ≤ 125_C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) 2.0 3.0 4.5 6.0 70 40 14 12 90 45 18 15 105 50 21 18 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns − 10 10 10 pF Cin Maximum Input Capacitance Typical @ 25°C, VCC = 5.0 V CPD 15 Power Dissipation Capacitance (Per Inverter)* pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . VCC TEST POINT tr tf 90% 50% 10% INPUT A VCC GND tPHL tPLH A OUTPUT DEVICE UNDER TEST Y CL* 90% 50% 10% OUTPUT Y tTHL tTLH Figure 1. Switching Waveforms *Includes all probe and jig capacitance Figure 2. Test Circuit http://onsemi.com 3 Figure 3. Logic Detail (1/6 of Device Shown) MC74HCU04A TYPICAL APPLICATIONS R2 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A R2 > > R1 C1 < C2 Vout R1 C C2 C1 R2 R1 Vout Figure 4. Crystal Oscillator Figure 5. Stable RC Oscillator VCC R2 1 M 1/6 HCU04A INPUT R2 > 6R1 R1 1/6 HCU04A OUTPUT 1/6 HCU04A Vin 1M Vout Figure 6. Schmitt Trigger Figure 7. High Input Impedance Single−Stage Amplifier with a 2 to 6 V Supply Range +V VCC 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A INPUT OUTPUT For reduced power supply current, use high−efficiency LEDs such as the Hewlett−Packard HLMP series or equivalent. Figure 8. Multi−Stage Amplifier Figure 9. LED Driver http://onsemi.com 4 MC74HCU04A ORDERING INFORMATION Package Shipping† MC74HCU04ADG SOIC−14 NB (Pb−Free) 55 Units / Rail NLV74HCU04ADG* SOIC−14 NB (Pb−Free) 55 Units / Rail MC74HCU04ADR2G SOIC−14 NB (Pb−Free) 2500 / Tape & Reel NLV74HCU04ADR2G* SOIC−14 NB (Pb−Free) 2500 / Tape & Reel MC74HCU04ADTR2G TSSOP−14 (Pb−Free) 2500 / Tape & Reel NLV74HCU04ADTR2G* TSSOP−14 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G ISSUE C 14 DATE 17 FEB 2016 1 SCALE 2:1 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− K1 J J1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX ALYWG G 7.06 1 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: 98ASH70246A DESCRIPTION: TSSOP−14 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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