MC74LCX125

MC74LCX125 Low−Voltage CMOS Quad Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) http://onsemi.com The MC74LCX125 is a high performance, non−inverting quad buffer operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX125 inputs to be safely driven from 5.0 V devices. The MC74LCX125 is suitable for memory address driving and all TTL level bus oriented transceiver applications. Current drive capability is 24 mA at the outputs. The Output Enable (OEn) inputs, when HIGH, disable the outputs by placing them in a HIGH Z condition. Features MARKING DIAGRAMS 14 14 1 SOIC−14 D SUFFIX CASE 751A 1 LCX125G AWLYWW • • • • • • • • • • • Designed for 2.3 to 3.6 V VCC Operation 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in all Three Logic States (10 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V Machine Model >200 V Pb−Free Packages are Available* 14 14 1 TSSOP−14 DT SUFFIX CASE 948G LCX 125 ALYWG G 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 1 May, 2005 − Rev. 5 Publication Order Number: MC74LCX125/D MC74LCX125 VCC 14 OE3 13 D3 12 O3 11 OE2 10 D2 9 O2 8 OE 0 D0 OE 1 D1 1 2 4 5 6 3 OE 2 O0 D2 OE 3 O1 D3 10 9 13 12 11 O3 8 O2 1 OE0 2 D0 3 O0 4 OE1 5 D1 6 O1 7 GND Figure 1. Pinout: 14−Lead (Top View) Figure 2. Logic Diagram PIN NAMES Pins OEn Dn On Function Output Enable Inputs Data Inputs 3−State Outputs TRUTH TABLE INPUTS OEn L L H Dn L H X OUTPUTS On L H Z H = High Voltage Level L = Low Voltage Level Z = High Impedance State X = High or Low Voltage Level and Transitions Are Acceptable; for ICC reasons, DO NOT FLOAT Inputs MAXIMUM RATINGS Symbol VCC VI VO Parameter DC Supply Voltage DC Input Voltage DC Output Voltage Value −0.5 to +7.0 −0.5 ≤ VI ≤ +7.0 −0.5 ≤ VO ≤ +7.0 −0.5 ≤ VO ≤ VCC + 0.5 IIK IOK DC Input Diode Current DC Output Diode Current −50 −50 +50 IO ICC IGND TSTG DC Output Source/Sink Current DC Supply Current Per Supply Pin DC Ground Current Per Ground Pin Storage Temperature Range ±50 ±100 ±100 −65 to +150 Output in 3−State Output in HIGH or LOW State. (Note 1) VI < GND VO < GND VO > VCC Condition Unit V V V V mA mA mA mA mA mA °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. http://onsemi.com 2 MC74LCX125 RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO IOH Supply Voltage Input Voltage Output Voltage HIGH Level Output Current (HIGH or LOW State) (3−State) VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V −40 0 Parameter Operating Data Retention Only Min 2.0 1.5 0 0 0 Typ 2.5, 3.3 2.5, 3.3 Max 3.6 3.6 5.5 VCC 5.5 − 24 − 12 −8 + 24 + 12 +8 +85 10 Unit V V V mA IOL LOW Level Output Current mA TA Dt/DV Operating Free−Air Temperature Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V °C ns/V DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol VIH Characteristic HIGH Level Input Voltage (Note 2) g( ) Condition 2.3 V ≤ VCC ≤ 2.7 V 2.7 V ≤ VCC ≤ 3.6 V VIL LOW Level Input Voltage (Note 2) g( ) 2.3 V ≤ VCC ≤ 2.7 V 2.7 V ≤ VCC ≤ 3.6 V VOH HIGH Level Output Voltage g 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA VCC = 2.3 V; IOH = −8 mA VCC = 2.7 V; IOH = −12 mA VCC = 3.0 V; IOH = −18 mA VCC = 3.0 V; IOH = −24 mA VOL LOW Level Output Voltage g 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA VCC = 2.3 V; IOL= 8 mA VCC = 2.7 V; IOL= 12 mA VCC = 3.0 V; IOL = 16 mA VCC = 3.0 V; IOL = 24 mA II ICC DICC Input Leakage Current Quiescent Supply Current y 2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V 2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC 2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V Increase in ICC per Input 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 2. These values of VI are used to test DC electrical characteristics only. VCC − 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 ±5 10 ±10 500 mA mA mA V Min 1.7 2.0 0.7 0.8 V V Max Unit V http://onsemi.com 3 MC74LCX125 AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 W Limits TA = −40°C to +85°C VCC = 3.3 V ± 0.3 V CL = 50 pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Propagation Delay Time Input to Output Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output−to−Output Skew (Note 3) Waveform 1 2 2 Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.0 6.0 7.0 7.0 6.0 6.0 1.0 1.0 VCC = 2.7 V CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.5 6.5 8.0 8.0 7.0 7.0 VCC = 2.5 V ± 0.2 V CL = 30 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 Max 7.2 7.2 9.1 9.1 7.2 7.2 Unit ns ns ns ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol VOLP VOLV Characteristic Dynamic LOW Peak Voltage (Note 4) Dynamic LOW Valley Voltage (Note 4) Condition VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V Min Typ 0.8 0.6 −0.8 −0.6 Max Unit V V V V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Condition VCC = 3.3 V, VI = 0 V or VCC VCC = 3.3 V, VI = 0 V or VCC 10 MHz, VCC = 3.3 V, VI = 0 V or VCC Typical 7 8 25 Unit pF pF pF ORDERING INFORMATION Device MC74LCX125D MC74LCX125DG MC74LCX125DR2 MC74LCX125DR2G MC74LCX125DT MC74LCX125DTG MC74LCX125DTR2 MC74LCX125DTR2G Package SOIC−14 SOIC−14 (Pb−Free) SOIC−14 SOIC−14 (Pb−Free) TSSOP−14* TSSOP−14* TSSOP−14* TSSOP−14* Shipping† 55 Units / Rail 55 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 96 Units / Rail 2500 Tape & Reel 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 4 MC74LCX125 VCC Dn Vmi Vmi 0V tPLH Vmo tPHL VOH On Vmo VOL WAVEFORM 1 − PROPAGATION DELAYS tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VCC OEn Vmi Vmi 0V tPZH Vmo ≈0V tPZL tPLZ ≈ 3.0 V tPHZ VCC VOH − 0.3 V On On Vmo VOL + 0.3 V GND WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VCC Symbol Vmi Vmo 3.3 V ± 0.3 V 1.5 V 1.5 V 2.7 V 1.5 V 1.5 V 2.5 V ± 0.2 V VCC/2 VCC/2 Figure 3. AC Waveforms VCC PULSE GENERATOR RT DUT CL RL CL = CL = RL = RT = 50 pF at VCC = 3.3 0.3 V or equivalent (includes jig and probe capacitance) 30 pF at VCC = 2.5 0.2 V or equivalent (includes jig and probe capacitance) R1 = 500 W or equivalent ZOUT of pulse generator (typically 50 W) Figure 4. Test Circuit http://onsemi.com 5 MC74LCX125 PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE G −A− 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 −B− P 7 PL 0.25 (0.010) M B M 1 7 G C R X 45 _ F −T− SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R http://onsemi.com 6 MC74LCX125 PACKAGE DIMENSIONS TSSOP−14 DT SUFFIX CASE 948G−01 ISSUE A 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B −U− N F DETAIL E K 0.15 (0.006) T U S J J1 C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E http://onsemi.com 7 ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ A −V− K1 SECTION N−N −W− DIM A B C D F G H J J1 K K1 L M MC74LCX125 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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