MC74LCX16374DTR2

MC74LCX16374 Low-Voltage CMOS 16-Bit D-Type Flip-Flop With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The MC74LCX16374 is a high performance, non−inverting 16−bit D−type flip−flop operating from a 2.3 V to 3.6 V supply. The device is byte controlled. Each byte has separate Output Enable and Clock Pulse inputs. These control pins can be tied together for full 16−bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX16374 inputs to be safely driven from 5.0 V devices. The MC74LCX16374 consists of 16 edge−triggered flip−flops with individual D−type inputs and 5.0 V−tolerant 3−state true outputs. The buffered clocks (CPn) and buffered Output Enables (OEn) are common to all flip−flops within the respective byte. The flip−flops will store the state of individual D inputs that meet the setup and hold time requirements on the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the contents of the flip−flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. The OE input level does not affect the operation of the flip−flops. Features • • • • • • • • • • • • Designed for 2.3 to 3.6 V VCC Operation 6.2 ns Maximum tpd 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V; Machine Model >200 V These are Pb−Free Devices* http://onsemi.com 48 1 TSSOP−48 DT SUFFIX CASE 1201 MARKING DIAGRAM 48 LCX16374G AWLYYWW 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2010 February, 2010 − Rev. 7 1 Publication Order Number: MC74LCX16374/D MC74LCX16374 1 OE1 1 48 CP1 O0 2 47 D0 O1 3 46 D1 GND 4 45 GND O2 5 44 D2 O3 6 43 D3 VCC 7 42 VCC O4 8 41 D4 O5 9 40 D5 GND 10 39 GND O6 11 38 D6 O7 12 37 D7 O8 13 36 D8 O9 14 35 D9 GND 15 34 GND O10 16 33 D10 O11 17 32 D11 VCC 18 31 VCC O12 19 30 D12 O13 20 29 D13 GND 21 28 GND O14 22 27 D14 O15 23 26 D15 OE2 24 25 CP2 24 OE1 CP1 OE2 48 CP2 2 nCP 47 D0 D2 O2 Q D3 O3 D5 O5 D6 O14 23 nCP 26 D15 D 22 Q D O7 Q O13 Q 27 12 nCP 20 nCP nCP O6 D14 37 O12 D 11 Q D D7 29 D13 nCP 38 19 Q D 9 D O11 Q 30 D12 Q 17 nCP nCP O4 nCP O10 Q D 8 Q D 40 32 D11 nCP 41 16 nCP D 6 Q D D4 33 D10 nCP O9 Q D 5 nCP D 43 35 D9 D 14 nCP O1 Q O8 Q D 3 nCP 44 36 D8 46 13 nCP O0 Q D D1 25 O15 Q D Figure 2. Logic Diagram Figure 1. Pinout: 48−Lead (Top View) Table 1. PIN NAMES Pins Function OEn CPn D0−D15 O0−O15 Output Enable Inputs Clock Pulse Inputs Inputs Outputs TRUTH TABLE Inputs H L Z ↑ X Outputs Inputs Outputs CP1 OE1 D0:7 O0:7 CP2 OE2 D8:15 O8:15 ↑ L H H ↑ L H H ↑ L L L ↑ L L L L L X O0 L L X O0 X H X Z X H X Z = = = = = High Voltage Level Low Voltage Level High Impedance State Low−to−High Transition High or Low Voltage Level and Transitions Are Acceptable; for ICC reasons, DO NOT FLOAT Inputs http://onsemi.com 2 MC74LCX16374 ORDERING INFORMATION Package Shipping† MC74LCX16374DT TSSOP−48* 39 Units / Rail MC74LCX16374DTG TSSOP−48* 39 Units / Rail MC74LCX16374DTR2 TSSOP−48* 2500 / Tape & Reel M74LCX16374DTR2G TSSOP−48* 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. MAXIMUM RATINGS Symbol VCC Parameter Value DC Supply Voltage Condition Unit −0.5 to +7.0 V V VI DC Input Voltage −0.5 ≤ VI ≤ +7.0 VO DC Output Voltage −0.5 ≤ VO ≤ +7.0 Output in 3−State −0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State. (Note 1) V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA +50 VO > VCC mA V IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Operating Data Retention Only Min Typ Max Unit 2.0 1.5 2.5, 3.3 2.5, 3.3 3.6 3.6 V 0 5.5 V 0 0 VCC 5.5 V VI Input Voltage VO Output Voltage IOH HIGH Level Output Current VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V − 24 − 12 −8 mA IOL LOW Level Output Current VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V + 24 + 12 +8 mA TA Operating Free−Air Temperature Dt/DV (HIGH or LOW State) (3−State) Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V http://onsemi.com 3 −55 +125 °C 0 10 ns/V MC74LCX16374 DC ELECTRICAL CHARACTERISTICS TA = −55°C to +125°C Symbol VIH VIL VOH VOL Condition Min 2.3 V ≤ VCC ≤ 2.7 V 1.7 2.7 V ≤ VCC ≤ 3.6 V 2.0 Characteristic HIGH Level Input Voltage (Note 2) LOW Level Input Voltage (Note 2) HIGH Level Output Voltage LOW Level Output Voltage Max V 2.3 V ≤ VCC ≤ 2.7 V 0.7 2.7 V ≤ VCC ≤ 3.6 V 0.8 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA VCC − 0.2 VCC = 2.3 V; IOH = −8 mA 1.8 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2.2 Unit V V 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA 0.2 VCC = 2.3 V; IOL= 8 mA 0.6 VCC = 2.7 V; IOL= 12 mA 0.4 VCC = 3.0 V; IOL = 16 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 V II Input Leakage Current 2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V ±5.0 mA IOZ 3−State Output Current 2.3 ≤ VCC ≤ 3.6 V; 0V ≤ VO ≤ 5.5 V; VI = VIH or V IL ±5.0 mA IOFF Power−Off Leakage Current VCC = 0 V; VI or VO = 5.5 V 10 mA ICC Quiescent Supply Current 2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC 20 mA 2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V ±20 mA 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 mA DICC Increase in ICC per Input 2. These values of VI are used to test DC electrical characteristics only. AC CHARACTERISTICS tR = tF = 2.5 ns; CL = 50 pF; RL = 500 W TA = −55°C to +125°C VCC = 3.3 V ± 0.3 V CL = 50 pF Symbol Parameter Waveform Min VCC = 2.7 V CL = 50 pF VCC = 2.5 V ± 0.2 V CL = 30 pF Max Min Max Min Max Unit fmax Clock Pulse Frequency 1 170 tPLH tPHL Propagation Delay CP to On 1 1.5 1.5 6.2 6.2 1.5 1.5 6.5 6.5 1.5 1.5 7.4 7.4 ns tPZH tPZL Output Enable Time to High and Low Level 2 1.5 1.5 6.1 6.1 1.5 1.5 6.3 6.3 1.5 1.5 7.9 7.9 ns tPHZ tPLZ Output Disable Time From High and Low Level 2 1.5 1.5 6.0 6.0 1.5 1.5 6.2 6.2 1.5 1.5 7.2 7.2 ns ts Setup Time, HIGH or LOW Dn to CP 1 2.5 2.5 3.0 ns th Hold Time, HIGH or LOW Dn to CP 1 1.5 1.5 2.0 ns tw CP Pulse Width, HIGH 3 3.0 3.0 3.5 ns tOSHL tOSLH Output−to−Output Skew (Note 3) MHz 1.0 1.0 ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 4 MC74LCX16374 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Min Condition Typ Max Unit VOLP Dynamic LOW Peak Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V 0.8 0.6 V V VOLV Dynamic LOW Valley Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V −0.8 −0.6 V V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol CIN Parameter Condition Typical Unit Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 20 pF VCC VCC Dn th ts 0V tPZH tPHZ VCC Vmo On Vmo VOH VHZ 0V fmax tPZL tPLH, tPHL On Vmi Vmi 0V CPn Vmi OEn tPLZ VOH Vmo On Vmo VHZ VOL VOL WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VCC CPn Vmi Vmi tw 0V VCC tw Vmo CPn Vmo 0V WAVEFORM 3 − PULSE WIDTH tR = tF = 2.5 ns (or fast as required) from 10% to 90%; Output requirements: VOL ≤ 0.8 V, VOH ≥ 2.0 V Figure 3. AC Waveforms Table 2. AC WAVEFORMS VCC Symbol 3.3 V ± 0.3 V 2.7 V 2.5 V + 0.2 V Vmi 1.5 V 1.5 V VCC / 2 Vmo 1.5 V 1.5 V VCC / 2 VHZ VOL + 0.3 V VOL + 0.3 V VOL + 0.15 V VLZ VOH − 0.3 V VOH − 0.3 V VOH − 0.15 V http://onsemi.com 5 MC74LCX16374 VCC R1 PULSE GENERATOR DUT RT CL RL Figure 4. Test Circuit Table 3. TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6 V at VCC = 3.3  0.3 V 6 V at VCC = 2.5  0.2 V Open Collector/Drain tPLH and tPHL 6V tPZH, tPHZ CL = CL = RL = RT = GND 50 pF at VCC = 3.3  0.3 V or equivalent (includes jig and probe capacitance) 30 pF at VCC = 2.5  0.2 V or equivalent (includes jig and probe capacitance) R1 = 500 W or equivalent ZOUT of pulse generator (typically 50 W) http://onsemi.com 6 6 V or VCC × 2 OPEN GND MC74LCX16374 PACKAGE DIMENSIONS TSSOP−48 DT SUFFIX CASE 1201−01 ISSUE A 48X K REF 0.12 (0.005) M T U S V S T U S J J1 25 0.254 (0.010) M 48 1 N 24 A −V− PIN 1 IDENT. ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N B −U− L N F DETAIL E D 0.076 (0.003) −T− SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. K K1 C M 0.25 (0.010) −W− G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 --1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 --0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.488 0.496 0.236 0.244 --0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 --0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_ DETAIL E H ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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