MC74LCX257

MC74LCX257 Low−Voltage CMOS Quad 2−Input Multiplexer With 5.0 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) http://onsemi.com The MC74LCX257 is a high performance, quad 2−input multiplexer with 3−state outputs operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX257 inputs to be safely driven from 5.0 V devices. Four bits of data from two sources can be selected using the Select input. The four outputs present the selected data in the true (non−inverted) form. The outputs may be switched to a high impedance state by placing a logic HIGH on the Output Enable (OE) input. Current drive capability is 24 mA at the outputs. Features MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 1 16 LCX257 AWLYWW 16 1 • • • • • • • • • • • 16 1 Designed for 2.3 to 3.6 V VCC Operation 5.0 V Tolerant − Interface Capability with 5.0 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V Machine Model >200 V Pb−Free Packages are Available* TSSOP−16 DT SUFFIX CASE 948F LCX 257 ALYW 1 16 SOEIAJ−16 M SUFFIX CASE 966 1 1 A L, WL Y W, WW = = = = Assembly Location Wafer Lot Year Work Week 74LCX257 ALYW 16 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 1 January, 2005 − Rev. 3 Publication Order Number: MC74LCX257/D MC74LCX257 VCC 16 OE 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9 I0a I1a I0b I1b 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b 7 Zb 8 GND I0c I1c I0d I1d 2 3 5 6 14 13 11 10 4 Za 7 Zb 12 Zc Figure 1. Pinout: 16−Lead Plastic Package (Top View) 9 Zd OE 15 S 1 Figure 2. Logic Diagram PIN NAMES Pins l0n l1n OE S Zn Function Source 0 Data Inputs Source 1 Data Inputs Output Enable Input Select Input Outputs TRUTH TABLE Inputs OE H L L L L H L X Z = = = = S X H H L L l0n X X X L H l1n X L H X X Outputs Zn Z L H L H High Voltage Level Low Voltage Level High or Low Voltage Level and Transitions are Acceptable High Impedance State For ICC reasons, DO NOT FLOAT Inputs http://onsemi.com 2 MC74LCX257 MAXIMUM RATINGS Symbol VCC VI VO Parameter DC Supply Voltage DC Input Voltage DC Output Voltage Value −0.5 to +7.0 −0.5 ≤ VI ≤ +7.0 −0.5 ≤ VI ≤ +7.0 −0.5 ≤ VO ≤ VCC + 0.5 IIK IOK DC Input Diode Current DC Output Diode Current −50 −50 +50 IO ICC IGND TSTG DC Output Source/Sink Current DC Supply Current Per Supply Pin DC Ground Current Per Ground Pin Storage Temperature Range ±50 ±100 ±100 −65 to +150 Output in 3−State Output in HIGH or LOW State (Note 1) VI < GND VO < GND VO > VCC Condition Unit V V V V mA mA mA mA mA mA °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO IOH Supply Voltage Input Voltage Output Voltage HIGH Level Output Current (HIGH or LOW State) (3−State) VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V −40 0 Parameter Operating Data Retention Only Min 2.0 1.5 0 0 0 Type 2.5, 3.3 2.5, 3.3 Max 3.6 3.6 5.5 VCC 5.5 −24 −12 −8 +24 +12 +8 +85 10 Unit V V V mA IOL LOW Level Output Current mA TA Dt/DV Operating Free−Air Temperature Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V °C ns/V ORDERING INFORMATION Device MC74LCX257DR2 MC74LCX257DR2G MC74LCX257DT MC74LCX257DTR2 MC74LCX257M MC74LCX257MEL Package SOIC−16 SOIC−16 (Pb−Free) TSSOP−16* TSSOP−16* SOEIAJ−16 SOEIAJ−16 Shipping† 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 48 Units / Rail 2000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 3 MC74LCX257 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol VIH Characteristic HIGH Level Input Voltage (Note 2) Condition 2.3 V ≤ VCC ≤ 2.7 V 2.7 V ≤ VCC ≤ 3.6 V VIL LOW Level Input Voltage (Note 2) 2.3 V ≤ VCC ≤ 2.7 V 2.7 V ≤ VCC ≤ 3.6 V VOH HIGH Level Output Voltage 2.3 V ≤ VCC ≤ 3.6 V; IOH = −100 mA VCC = 2.3 V; IOH = −8 mA VCC = 2.7 V; IOH = −12 mA VCC = 3.0 V; IOH = −18 mA VCC = 3.0 V; IOH = −24 mA VOL LOW Level Output Voltage 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA VCC = 2.3 V; IOL = 8 mA VCC = 2.7 V; IOL = 12 mA VCC = 3.0 V; IOL = 16 mA VCC = 3.0 V; IOL = 24 mA II IOZ IOFF ICC Input Leakage Current 3−State Output Current Power−Off Leakage Current Quiescent Supply Current 2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V 2.3 ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 5.5 V; VI = VIH or VIL VCC = 0 V; VI or VO = 5.5 V 2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC 2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V DICC Increase in ICC per Input 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 2. These values of VI are used to test DC electrical characteristics only. VCC − 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 ±5 ±5 10 10 ±10 500 mA mA mA mA mA V Min 1.7 2.0 0.7 0.8 V V Max Unit V AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 W Limits TA = −40°C to +85°C VCC = 3.3 V ± 0.3 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Propagation Delay In to Zn Propagation Delay S to Zn Output Enable Time to High and Low Level Output Disable Time From High and Low Level Output−to−Output Skew (Note 3) 3 3 1, 2 Waveform 1 Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.0 6.0 7.0 7.0 7.0 7.0 5.5 5.5 1.0 1.0 VCC = 2.7 V CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.5 6.5 8.5 8.5 8.5 8.5 6.0 6.0 VCC = 2.5 V ± 0.2 V CL = 30 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 7.2 7.2 9.1 9.1 9.1 9.1 6.6 6.6 ns ns ns ns Unit ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 4 MC74LCX257 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol VOLP VOLV Characteristic Dynamic LOW Peak Voltage (Note 4) Dynamic LOW Valley Voltage (Note 4) Condition VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V Min Typ 0.8 0.6 −0.8 −0.6 Max Unit V V V V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Condition VCC = 3.3 V, VI = 0 V or VCC VCC = 3.3 V, VI = 0 V or VCC 10 MHz, VCC = 3.3 V, VI = 0 V or VCC Typical 7 8 25 Unit pF pF pF VCC In, S Vmi Vmi 0V tPLH Vmo tPHL VOH Zn Vmo VOL WAVEFORM 1 − NON−INVERTING PROPAGATION DELAYS tR = tF = 2.5 ns, 10% to 90%; f = 1.0 MHz; tW = 500 ns Zn Vmo Vmo tPLH tPHL S Vmi Vmi VCC 0V VOH VOL WAVEFORM 2 − INVERTING PROPAGATION DELAYS tR = tF = 2.5 ns, 10% to 90%; f = 1.0 MHz; tW = 500 ns VCC OE Vmi Vmi 0V tPZH Vmo tPHZ VCC VOH − 0.3 V ≈0V tPZL tPLZ ≈ 3.0V Zn Zn Vmo VOL + 0.3 V GND WAVEFORM 3 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1.0 MHz; tW = 500 ns Vcc Symbol Vmi Vmo VHZ VLZ 3.3 V + 0.3 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 2.5 V + 0.2 V Vcc/2 Vcc/2 VOL + 0.15 V VOH − 0.15 V Figure 3. AC Waveforms http://onsemi.com 5 MC74LCX257 PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 −A− 16 9 −B− 1 8 P 8 PL 0.25 (0.010) M B S G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE O 16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 2X L/2 9 J1 B −U− L PIN 1 IDENT. 1 8 SECTION N−N J N 0.15 (0.006) T U S 0.25 (0.010) M A −V− N F DETAIL E C 0.10 (0.004) −T− SEATING PLANE H D G DETAIL E http://onsemi.com 6 ÉÉ ÇÇ ÉÉ ÇÇ −W− MC74LCX257 PACKAGE DIMENSIONS SOEIAJ−16 M SUFFIX CASE 966−01 ISSUE O 16 9 LE Q1 E HE M_ L DETAIL P 1 8 Z D e A VIEW P c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.78 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.031 b 0.13 (0.005) M A1 0.10 (0.004) http://onsemi.com 7 MC74LCX257 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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