MC74LV594A
8-Bit Shift Register with
Output Register
The MC74LV594A is an 8−bit shift register designed for
2 V to 6.0 V VCC operation. The device contain an 8−bit serial−in,
parallel−out shift register that feeds an 8−bit D−type storage register.
Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR,
SRCLR) inputs are provided on the shift and storage registers. A serial
output (QH’) is provided for cascading purposes.
The shift−register (SRCLK) and storage−register (RCLK) clocks
are positive−edge triggered. If the clocks are tied together, the shift
register always is one clock pulse ahead of the storage register.
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16
•
•
•
•
•
•
•
•
•
•
•
•
SOIC−16
D SUFFIX
CASE 751B
16
1
Features
2.0 V to 6.0 V VCC Operation
Low Input Current: 1.0 mA
Max tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2.3 V
at VCC = 3.3 V, TA = 25°C
Support Mixed−Mode Voltage Operation on All Ports
8−Bit Serial−In, Parallel−Out Shift Registers With Storage
Independent Direct Overriding Clears on Shift and Storage Registers
Independent Clocks for Shift and Storage Registers
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING
DIAGRAMS
LV594AG
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
16
LV
594A
ALYWG
G
1
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
QB
1
16
VCC
QC
2
15
QA
QD
3
14
SER
QE
4
13
RCLR
QF
5
12
RCLR
QG
6
11
SRCLR
QH
7
10
SRCLR
GND
8
9
QH’
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
May, 2018 − Rev. 2
1
Publication Order Number:
MC74LV594A/D
MC74LV594A
FUNCTION TABLE
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2
MC74LV594A
Figure 1. Logic Diagram
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3
MC74LV594A
Figure 2. Timing Diagram
ORDERING INFORMATION
Package
Shipping†
MC74LV594ADR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74LV594ADTR2G
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74LV594A
MAXIMUM RATINGS
Symbol
VCC
Parameter
DC Supply Voltage
Value
Unit
−0.5 to +7.0
V
VI
DC Input Voltage
−0.5 to VCC + 0.5
V
VO
DC Output Voltage Active Mode (Note 1)
−0.5 to VCC + 0.5
V
High Impedance or Power−Off Mode
−0.5 to +7.0
IIK
DC Input Clamp Current
±20
mA
IOK
DC Output Clamp Current
±35
mA
IIN
DC Input Current
±20
mA
IO
DC Output Source / Sink Current
±35
mA
ICC
DC Supply Current per Supply Pin
±75
mA
IGND
DC Ground Current per Ground Pin
±75
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction temperature under Bias
+150
°C
qJA
Thermal Resistance SOIC
TSSOP
112
148
°C
PD
Power Dissipation in Still Air at SOIC
TSSOP
500
450
mW
MSL
FR
VESD
ILatchup
Moisture Sensitivity
Level 1
Flammability Rating Oxygen Index: 30% − 35%
UL−94−VO (0.125 in)
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Latchup Performance Above VCC and Below GND at 85°C (Note 5)
> 3000
>400
N/A
V
±300
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS (Note 6)
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
VI
DC Input Voltage (Referenced to GND)
VO
DC Output Voltage (Referenced to GND)
TA
Operating Free−Air Temperature
tr, tf
Input Rise or Fall Rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
0
VCC
V
−55
+85
°C
0
0
0
1000
500
400
nS
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
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5
MC74LV594A
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limits
TA = 255C
Symbol
Parameter
VIH
Minimum
High−Level Input Voltage
VIL
Maximum
Low−Level Input Voltage
Conditions
Typ
TA = −555C to 1255C
VCC, (V)
Min
Max
Min
2.0
1.5
1.5
2.3 – 6.0
0.7 x VCC
0.7 x VCC
Max
Unit
V
2.0
0.5
0.5
2.3 – 6.0
0.3 x VCC
0.3 x VCC
V
VIN = VIH or VIL
VOH
Minimum
High−Level
Output Voltage
IoH = −50 mA
2.0 – 6.0
VCC – 0.1
VCC –
0.1
IoH = −2 mA
2.3
2
2
IoH = −6 mA
3.0
2.48
2.48
IoH = −12 mA
4.5
3.8
3.8
V
VIN = VIH or VIL
VOL
Maximum
Low−Level
Output Voltage
IoH = 50 mA
2.0 – 6.0
IoH = 2 mA
2.3
0.4
0.4
IoH = 6 mA
3.0
0.44
0.44
IoH = 12 mA
4.5
0.55
0.55
VI = VCC or
GND
6.0
IIN
Maximum Input Leakage
Current
ICC
Maximum Supply Current
VI = VCC or
GND, IO = 0 A
6.0
CI
Input Capacitance
VI = VCC or
GND
3.3
0.1
±0.1
±1
8.0
3.5
0.1
V
mA
80
mA
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
MC74LV594A
TIMING SPECIFICATIONS (See Figure 3)
TA = 255C
Symbol
tW
Parameter
Pulse Duration
Conditions
VCC, (V)
RCLK or SRCLK
High or Low
2.3 – 2.7
7
7.5
3.0 – 3.6
5.5
5.5
4.5 – 5.5
5
5
2.3 – 2.7
6
6.5
RCLR or SRCLR Low
SER before SRCLK↑
SRCLK↑ before
RCLK↑
SRCLR Low before
RCLK↑
tSU
Setup Time
SRCLR High (Inactive)
before
SRCLK↑
RCLR High (Inactive)
before RCLK↑
tH
Hold Time
SER after SRCLK↑
Min
3.0 – 3.6
5
5
4.5 – 5.5
5.2
5.2
2.3 – 2.7
5.5
5.5
3.0 – 3.6
3.5
3.5
4.5 – 5.5
3
3
2.3 – 2.7
8
9
3.0 – 3.6
8
8.5
4.5 – 5.5
5
5
2.3 – 2.7
8.5
9.5
3.0 – 3.6
8
9
4.5 – 5.5
5
5
2.3 – 2.7
6
6.8
3.0 – 3.6
4.2
4.8
4.5 – 5.5
2.9
3.3
2.3 – 2.7
6.7
7.6
3.0 – 3.6
4.6
5.3
4.5 – 5.5
3.2
3.7
2.3 – 2.7
1.5
1.5
3.0 – 3.6
1.5
1.5
4.5 – 5.5
2
2
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7
Max
TA = −555C to 1255C
Min
Max
Unit
ns
ns
ns
MC74LV594A
AC CHARACTERISTICS (See Figure 3)
Guaranteed Limits
Symbol
Paraeter
Load
Conditions
Input to Output
CL = 15 pF
fMAX
CL = 50 pF
RCLK to
QA−QH
CL = 15 pF
SRCLK to QH’
tPLH
TA = −555C to
1255C
TA = 255C
Propagation
Delay Low to
High
RCLK to
QA−QH
CL = 50 pF
SRCLK to QH’
RCLK to
QA−QH
SRCLK to QH’
CL = 15 pF
RCLR to
QA−QH
VCC, (V)
Min
Typ
Max
2.3 – 2.7
65
80
45
3.0 – 3.6
80
120
70
4.5 – 5.5
135
170
115
2.3 – 2.7
50
51
40
3.0 – 3.6
70
74
55
4.5 – 5.5
115
120
tPHL
Propagation
Delay High to
Low
RCLK to
QA−QH
SRCLK to QH’
CL = 50 pF
RCLR to
QA−QH
SRCLR to QH’
Max
90
27.5
1
32.5
3.0 – 3.6
18
1
22.5
4.5 – 5.5
12
1
15
2.3 – 2.7
27.5
1
32
3.0 – 3.6
18
1
22
4.5 – 5.5
12.5
1
12
2.3 – 2.7
22.1
25.0
1
30.0
3.0 – 3.6
15.6
17.5
1
21.0
4.5 – 5.5
11.5
12.5
1
15.5
2.3 – 2.7
21.6
25.5
1
29.5
3.0 – 3.6
15.2
18.0
1
21.0
4.5 – 5.5
10.9
12.5
1
15.0
2.3 – 2.7
23
1
27.5
3.0 – 3.6
15.5
1
19
4.5 – 5.5
11
1
14
2.3 – 2.7
23.5
1
27
3.0 – 3.6
16
1
19
4.5 – 5.5
11
1
13.5
2.3 – 2.7
20.5
1
25
3.0 – 3.6
14.5
1
17.5
4.5 – 5.5
10
1
12
1
23
3.0 – 3.6
13
1
16
4.5 – 5.5
9
1
11
2.3 – 2.7
19.7
23.0
1
27.0
3.0 – 3.6
14.0
16.5
1
19.5
4.5 – 5.5
10.1
11.5
1
13.5
2.3 – 2.7
18.4
21.5
1
25.0
3.0 – 3.6
13.1
15.0
1
18.0
4.5 – 5.5
9.0
10.5
1
12.5
2.3 – 2.7
25.7
30.0
1
35.0
3.0 – 3.6
17.6
20.0
1
24.5
4.5 – 5.5
12.2
13.5
1
17.0
2.3 – 2.7
25.3
30.0
1
34
3.0 – 3.6
17.3
20.0
1
24.0
4.5 – 5.5
11.9
14.0
1
16.5
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8
Unit
MHz
2.3 – 2.7
2.3 – 2.7
SRCLR to QH’
Min
ns
ns
MC74LV594A
NOISE CHARACTERISTICS, VCC = 3.3 V, CL = 50 pF, TA = 25°C
Symbol
Typ
Max
Unit
VOL(P)
Quiet Output, Maximum Dynamic VOL
Parameter
Min
0.8
0.8
V
VOL(V)
Quiet Output, Minimum Dynamic VOL
−0.1
−0.8
V
VOH(V)
Quiet Output, Minimum Dynamic VOH
2.8
VIH(D)
High−Level Dynamic Input Voltage
VIL(D)
Low−Level Dynamic Input Voltage
V
2.31
V
0.99
V
POWER DISSIPATION CHARACTERISTICS, TA = 25°C
Symbol
CPD
Parameter
Test Conditions
VCC (V)
Typ
Unit
f = 10 MHz
3.3
93
pF
5
112
Power Dissipation Capacitance
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9
MC74LV594A
Figure 3. Load Circuit and Voltage Waveforms
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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onsemi,
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