MC74LVX374
Octal D-Type Flip-Flop
with 3-State Outputs
With 5V−Tolerant Inputs
The MC74LVX374 is an advanced high speed CMOS octal D−type
flip−flop with 3−state outputs. The inputs tolerate voltages up to 7.0 V,
allowing the interface of 5.0 V systems to 3.0 V systems.
This 8−bit D−type flip−flop is controlled by a clock input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
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SOIC−20
DW SUFFIX
CASE 751D
Features
•
•
•
•
•
•
•
•
•
High Speed: fmax = 160 MHz (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
These Devices are Pb−Free and are RoHS Compliant
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
VCC O7 D7
20 19 18
1
2
D6 O6 O5 D5
17 16 15 14
3
4
OE O0 D0
5
6
D4 O4
13 12
7
8
D1 O1 O2 D2
9
CP
11
10
D3 O3 GND
20−Lead (Top View)
MARKING DIAGRAMS
20
20
LVX
374
ALYWG
G
LVX374
AWLYYWWG
1
1
SOIC−20
LVX374
A
WL, L
Y
WW, W
G or G
TSSOP−20
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN NAMES
Pins
Function
OE
CP
D0−D7
O0−O7
Output Enable Input
Clock Pulse Input
Data Inputs
3−State Outputs
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 4
1
Publication Order Number:
MC74LVX374/D
MC74LVX374
OE
CP
1
11
2
nCP
3
O0
Q
D0
D
5
nCP
4
O1
Q
D1
D
6
nCP
7
O2
Q
D2
D
9
nCP
8
O3
Q
D3
D
12
nCP
13
O4
Q
D4
D
15
nCP
14
O5
Q
D5
D
16
nCP
17
O6
Q
D6
D
19
nCP
18
O7
Q
D7
D
Figure 1. Logic Diagram
INPUTS
OUTPUTS
OE
CP
Dn
On
OPERATING MODE
L
L
↑
↑
l
h
L
H
Load and Read Register
L
↑
X
NC
Hold and Read Register
H
↑
X
Z
Hold and Disable Outputs
H
H
↑
↑
l
h
Z
Z
Load Internal Register and Disable Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition; L = Low
Voltage Level; l = Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition; NC = No Change,
State Prior to Low−to−High Clock Transition; X = High or Low Voltage Level and Transitions are Acceptable; Z = High
Impedance State; ↑ = Low−to−High Transition; ↑ = Not a Low−to−High Transition; For ICC Reasons DO NOT FLOAT
Inputs
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2
MC74LVX374
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation
180
mW
Tstg
Storage Temperature
–65 to +150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
3.6
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
−40
+85
_C
0
100
ns/V
TA
Dt/DV
Operating Temperature, All Package Types
Input Rise and Fall Time
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
V
Min
1.5
2.0
2.4
VIH
High−Level Input Voltage
2.0
3.0
3.6
VIL
Low−Level Input Voltage
2.0
3.0
3.6
VOH
High−Level Output Voltage
(Vin = VIH or VIL)
IOH = −50 mA
IOH = −50 mA
IOH = −4 mA
2.0
3.0
3.0
VOL
Low−Level Output Voltage
(Vin = VIH or VIL)
IOL = 50 mA
IOL = 50 mA
IOL = 4 mA
2.0
3.0
3.0
Iin
Input Leakage Current
Vin = 5.5 V or GND
IOZ
Maximum 3−State Leakage Current
ICC
Quiescent Supply Current
Typ
TA = −40 to 85°C
Max
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.58
Max
2.0
3.0
0.0
0.0
Unit
V
0.5
0.8
0.8
1.9
2.9
2.48
V
V
0.1
0.1
0.36
0.1
0.1
0.44
V
3.6
±0.1
±1.0
mA
Vin = VIL or VIH
Vout = VCC or GND
3.6
±0.2
5
±2.5
mA
Vin = VCC or GND
3.6
4.0
40.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
MC74LVX374
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
fmax
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSHL
tOSLH
Parameter
Test Conditions
Maximum Clock Frequency
(50% Duty Cycle)
Propagation Delay
CP to O
Output Enable Time
OE to O
Output Disable Time
OE to O
Output−to−Output Skew
(Note 1)
Min
Typ
TA = −40 to 85°C
Max
Min
Max
VCC = 2.7 V
CL = 15 pF
CL = 50 pF
60
45
115
60
50
40
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
100
60
160
95
85
55
VCC = 2.7 V
CL = 15 pF
CL = 50 pF
8.5
11.0
16.3
19.8
1.0
1.0
19.5
23.0
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
6.7
9.2
10.6
14.1
1.0
1.0
12.5
16.0
VCC = 2.7 V
RL = 1 kW
CL = 15 pF
CL = 50 pF
7.6
10.1
14.5
18.0
1.0
1.0
17.5
21.0
VCC = 3.3 ± 0.3 V
RL = 1 kW
CL = 15 pF
CL = 50 pF
5.9
8.4
9.3
12.8
1.0
1.0
11.0
14.5
VCC = 2.7 V
RL = 1 kW
CL = 50 pF
11.5
18.5
1.0
22.0
VCC = 3.3 ± 0.3 V
RL = 1 kW
CL = 50 pF
9.6
13.2
1.0
15.0
VCC = 2.7 V
VCC = 3.3 ± 0.3 V
CL = 50 pF
CL = 50 pF
Unit
MHz
1.5
1.5
1.5
1.5
ns
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
TA = 25°C
Symbol
Min
Parameter
TA = −40 to 85°C
Typ
Max
10
Min
Max
Unit
10
pF
Cin
Input Capacitance
4
Cout
Maximum Three−State Output Capacitance
6
pF
CPD
Power Dissipation Capacitance (Note 2)
32
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per flip−flop). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25°C
Characteristic
Symbol
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.5
−0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
Test Conditions
Typ
TA = −40 to 85°C
Limit
Limit
Unit
tw
Minimum Pulse Width, CP
VCC = 2.7 V
VCC = 3.3 ± 0.3 V
7.5
5.0
8.0
5.5
ns
tsu
Minimum Setup Time, D to CP
VCC = 2.7 V
VCC = 3.3 ± 0.3 V
6.5
4.5
6.5
4.5
ns
th
Minimum Hold Time, D to CP
VCC = 2.7 V
VCC = 3.3 ± 0.3 V
2.0
2.0
2.0
2.0
ns
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4
MC74LVX374
SWITCHING WAVEFORMS
VCC
OE
VCC
CP
50%
GND
50%
tPZL
GND
tW
tPLH
O
HIGH
IMPEDANCE
50% VCC
O
1/fmax
tPLZ
VOL +0.3V
tPHL
tPZH
50% VCC
tPHZ
VOH -0.3V
O
50% VCC
Figure 2.
HIGH
IMPEDANCE
Figure 3.
VALID
VCC
50%
D
GND
th
tsu
VCC
CP
50%
GND
Figure 4.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Propagation Delay Test Circuit
Figure 6. Three−State Test Circuit
ORDERING INFORMATION
Package
Shipping†
MC74LVX374DWR2G
SOIC−20
(Pb−Free)
1000 Tape & Reel
MC74LVX374DTR2G
TSSOP−20
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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