MC74LVX574DT

MC74LVX574 Octal D-Type Flip-Flop with 3-State Outputs The MC74LVX574 is an advanced high speed CMOS octal flip−flop with 3−state outputs. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. This 8−bit D−type flip−flop is controlled by a clock pulse input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. http://onsemi.com Features • • • • • • • • • High Speed: tPD = 8.5 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V These Devices are Pb−Free and are RoHS Compliant D0 D1 D2 D3 2 C Q D 19 3 C Q D 18 4 C Q D 17 5 C Q D 16 SOIC−20 DW SUFFIX CASE 751D PIN ASSIGNMENT VCC O0 O1 O2 O3 O4 O5 O6 O7 CP 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND 20−Lead (Top View) Q0 MARKING DIAGRAMS Q1 20 20 D5 D6 D7 6 C Q D 15 7 C Q D 14 8 C Q D 13 C Q D 9 CP OE LVX 574 ALYWG G LVX574 AWLYYWWG Q2 1 1 Q3 SOIC−20 D4 TSSOP−20 DT SUFFIX CASE 948E LVX574 A WL, L Y WW, W G or G Q4 Q5 TSSOP−20 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Q6 ORDERING INFORMATION 12 See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Q7 11 1 Figure 1. Logic Diagram © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 4 1 Publication Order Number: MC74LVX574/D MC74LVX574 PIN NAMES Pins Function OE CP D0−D7 O0−O7 Output Enable Input Clock Pulse Input Data Inputs 3−State Latch Outputs FUNCTION TABLE INPUTS OE L L L H OUTPUT CP D Q L, H, X H L X X H L No Change Z MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage Parameter –0.5 to +7.0 V Vin DC Input Voltage –0.5 to +7.0 V Vout DC Output Voltage –0.5 to VCC +0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation 180 mW Tstg Storage Temperature –65 to +150 _C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage 2.0 3.6 V Vin DC Input Voltage 0 5.5 V Vout DC Output Voltage 0 VCC V −40 +85 _C 0 100 ns/V TA Dt/DV Operating Temperature, All Package Types Input Rise and Fall Time Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 2 MC74LVX574 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions TA = 25°C VCC V Min 1.5 2.0 2.4 VIH High−Level Input Voltage 2.0 3.0 3.6 VIL Low−Level Input Voltage 2.0 3.0 3.6 VOH High−Level Output Voltage (Vin = VIH or VIL) IOH = −50 mA IOH = −50 mA IOH = −4 mA 2.0 3.0 3.0 VOL Low−Level Output Voltage (Vin = VIH or VIL) IOL = 50 mA IOL = 50 mA IOL = 4 mA 2.0 3.0 3.0 Iin Input Leakage Current Vin = 5.5 V or GND IOZ Maximum 3−State Leakage Current ICC Quiescent Supply Current Typ TA = −40 to 85°C Max Min 0.5 0.8 0.8 1.9 2.9 2.58 Max 1.5 2.0 2.4 2.0 3.0 0.0 0.0 Unit V 0.5 0.8 0.8 1.9 2.9 2.48 V V 0.1 0.1 0.36 0.1 0.1 0.44 V 3.6 ±0.1 ±1.0 mA Vin = VIL or VIH Vout = VCC or GND 3.6 ±0.2 5 ±2.5 mA Vin = VCC or GND 3.6 4.0 40.0 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Symbol fmax tPLH, tPHL tPZL, tPZH tPLZ, tPHZ tOSHL tOSLH Parameter Maximum Clock Frequency (50% Duty Cycle) Propagation Delay CP to O Output Enable Time OE to O Output Disable Time OE to O Output−to−Output Skew (Note 1) TA = −40 to 85°C Min Typ VCC = 2.7 V CL = 15 pF CL = 50 pF 60 45 115 60 50 40 VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 80 50 125 75 65 45 VCC = 2.7 V CL = 15 pF CL = 50 pF 9.2 11.5 14.5 18.0 1.0 1.0 17.5 21.0 VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 8.5 11.0 13.2 16.7 1.0 1.0 15.5 19.0 VCC = 2.7 V RL = 1 kW CL = 15 pF CL = 50 pF 9.8 11.4 15.0 18.5 1.0 1.0 18.5 22.0 VCC = 3.3 ± 0.3 V RL = 1 kW CL = 15 pF CL = 50 pF 8.2 10.7 12.8 16.3 1.0 1.0 15.0 18.5 VCC = 2.7 V RL = 1 kW CL = 50 pF 12.1 19.1 1.0 22.0 VCC = 3.3 ± 0.3 V RL = 1 kW CL = 50 pF 11.0 15.0 1.0 17.0 VCC = 2.7 V VCC = 3.3 ± 0.3 V CL = 50 pF CL = 50 pF Test Conditions Max 1.5 1.5 Min Max Unit ns 1.5 1.5 ns ns ns ns 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 3 MC74LVX574 CAPACITIVE CHARACTERISTICS TA = 25°C Symbol Min Parameter TA = −40 to 85°C Typ Max 10 Min Max Unit 10 pF Cin Input Capacitance 4 Cout Maximum Three−State Output Capacitance 6 pF CPD Power Dissipation Capacitance (Note 2) 28 pF 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 8 (per latch). CPD is used to determine the no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package) TA = 25°C Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.5 0.8 V VOLV Quiet Output Minimum Dynamic VOL −0.5 −0.8 V VIHD Minimum High Level Dynamic Input Voltage 2.0 V VILD Maximum Low Level Dynamic Input Voltage 0.8 V Symbol Characteristic TIMING REQUIREMENTS (Input tr = tf = 3.0ns) TA = 25°C Limit Limit Unit Minimum Pulse Width, CP VCC = 2.7 V VCC = 3.3 ± 0.3 V 6.5 5.0 7.5 5.0 ns tsu Minimum Setup Time, D to CP VCC = 2.7 V VCC = 3.3 ± 0.3 V 5.0 3.5 5.0 3.5 ns th Minimum Hold Time, D to CP VCC = 2.7 V VCC = 3.3 ± 0.3 V 1.5 1.5 1.5 1.5 ns Symbol tw(h) Parameter Typ TA = −40 to 85°C Test Conditions SWITCHING WAVEFORMS VCC CP 50% GND tw 1/fmax tPLH Q tPHL 50% VCC Figure 2. VCC OE 50% VOL +0.3V GND tPZL O 50% VCC tPZH O tPLZ VALID VCC HIGH VOL -0.3V IMPEDANCE D 50% GND tsu tPHZ 50% VCC CP th VCC 50% GND HIGH IMPEDANCE Figure 3. Figure 4. http://onsemi.com 4 MC74LVX574 TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 5. Propagation Delay Test Circuit Figure 6. Three−State Test Circuit ORDERING INFORMATION Package Shipping† MC74LVX574DWR2G SOIC−20 (Pb−Free) 1000 Tape & Reel MC74LVX574DTG TSSOP−20 (Pb−Free) 75 Units / Rail MC74LVX574DTR2G TSSOP−20 (Pb−Free) 2500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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