MC74VHC1GT04
Inverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT04 is a single gate inverting buffer fabricated with
silicon gate CMOS technology. It achieves high speed operation similar
to equivalent Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and the
output has a full 5.0 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT04 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT04 to be used to interface 5.0 V circuits to 3.0 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
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MARKING
DIAGRAMS
5
SC−88A
DF SUFFIX
CASE 419A
VKd
1
TSOP−5
DT SUFFIX
CASE 483
5
VKd
1
VK = Specific Device Code
d = Date Code
High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 1 A (Max) at TA = 25°C
PIN ASSIGNMENT
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @ Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
1
NC
2
IN A
3
GND
4
OUT Y
5
VCC
Chip Complexity: FETs = 105; Equivalent Gates = 26
Pb−Free Package is Available
NC
1
IN A
2
GND
3
5
VCC
4
OUT Y
FUNCTION TABLE
1
Y Output
L
H
H
L
ORDERING INFORMATION
Figure 1. Pinout (Top View)
IN A
A Input
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
OUT Y
Figure 2. Logic Symbol
Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 10
1
Publication Order Number:
MC74VHC1GT04/D
MC74VHC1GT04
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
VCC
DC Supply Voltage
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to 7.0
−0.5 to VCC + 0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
+20
mA
IOUT
DC Output Current, per Pin
+25
mA
ICC
DC Supply Current, VCC and GND
+50
mA
PD
Power dissipation in still air
SC−88A, TSOP−5
200
mW
JA
Thermal resistance
SC−88A, TSOP−5
333
C/W
TL
Lead temperature, 1 mm from case for 10 s
260
°C
TJ
Junction temperature under bias
+150
°C
Tstg
Storage temperature
−65 to +150
°C
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 1500
> 200
N/A
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 125°C (Note 4)
±500
mA
VCC = 0
High or Low State
VOUT < GND; VOUT > VCC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
DC Supply Voltage
3.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
VOUT
DC Output Voltage
0.0
0.0
5.5
VCC
V
TA
Operating Temperature Range
−55
+125
°C
tr , tf
Input Rise and Fall Time
0
0
100
20
ns/V
VCC = 0
High or Low State
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
80
TJ = 90 ° C
Time, Years
TJ = 100 ° C
Time, Hours
TJ = 110° C
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 120° C
Device Junction Temperature versus
Time to 0.1% Bond Failures
TJ = 130 ° C
NORMALIZED FAILURE RATE
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
1
1
10
100
TIME, YEARS
Figure 3. Failure Rate vs. Time
Junction Temperature
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2
1000
MC74VHC1GT04
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
1.4
2.0
2.0
VIH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
VOH
Minimum High−Level
Output Voltage
VIN = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA ≤ 85°C
TA = 25°C
VCC
(V)
Typ
Max
Min
3.0
4.5
2.9
4.4
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 A
3.0
4.5
VIN = VIH or VIL
IOL = 4.0 mA
IOL = 8.0 mA
Max
1.4
2.0
2.0
0.53
0.8
0.8
VIN = VIH or VIL
IOH = −50 A
−55 ≤ TA ≤ 125°C
3.0
4.5
Min
Max
1.4
2.0
2.0
0.53
0.8
0.8
V
0.53
0.8
0.8
2.9
4.4
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
V
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
A
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
A
ICCT
Quiescent Supply
Current
Input: VIN = 3.4 V
5.5
1.35
1.50
1.65
mA
IOPD
Output Leakage
Current
VOUT = 5.5 V
0.0
0.5
5.0
10
A
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AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns
TA ≤ 85°C
TA = 25°C
Symbol
tPLH,
tPHL
CIN
Parameter
Maximum
Propagation
Delay,
g
y
I
Input
t A to
t Y
Min
Test Conditions
Typ
Max
Min
−55 ≤ TA ≤ 125°C
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
5.0
6.2
10.0
13.5
11.0
15.0
13.0
17.5
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
3.8
4.2
6.7
7.7
7.5
8.5
8.5
9.5
5.0
10
10
10
Maximum Input
Capacitance
pF
Typical @ 25°C, VCC = 5.0 V
CPD
10
Power Dissipation Capacitance (Note 5)
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74VHC1GT04
TEST POINT
3.0 V
A
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
tPHL
CL *
VOH
Y
50% VCC
VOL
*Includes all probe and jig capacitance
Figure 4. Switching Waveforms
Figure 5. Test Circuit
DEVICE ORDERING INFORMATION
Device Nomenclature
Device
Order Number
Circuit
Indicator
Temp
Range
Identifier
Technology
Device
Function
Package
Suffix
Tape &
Reel
Suffix
Package
Type
Package†
MC74VHC1GT04DFT1
MC
74
VHC1G
T04
DF
T1
SC−88A
3000 / Tape & Reel
178 mm (7 inch)
MC74VHC1GT04DFT2
MC
74
VHC1G
T04
DF
T2
SC−88A
3000 / Tape & Reel
178 mm (7 inch)
MC74VHC1GT04DTT1
MC
74
VHC1G
T04
DT
T1
TSOP−5
3000 / Tape & Reel
178 mm (7 inch)
MC74VHC1GT04DF2G
MC
74
VHC1G
T04
DT
T1
SC−88A
(Pb−Free)
3000 / Tape & Reel
178 mm (7 inch)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1GT04
PACKAGE DIMENSIONS
SC−88A−5 / SOT−353 / SC−70−5
DF SUFFIX
CASE 419A−02
ISSUE G
A
G
5
4
DIM
A
B
C
D
G
H
J
K
N
S
−B−
S
1
2
3
D 5 PL
0.2 (0.008)
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
−−−
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm
inches
SC−88A/SC70−5/SOT−353
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
−−−
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1GT04
PACKAGE DIMENSIONS
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
5−LEAD PACKAGE
CASE 483−02
ISSUE C
D
S
5
4
1
2
3
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
L
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
2.90
3.10 0.1142 0.1220
B
1.30
1.70 0.0512 0.0669
C
0.90
1.10 0.0354 0.0433
D
0.25
0.50 0.0098 0.0197
G
0.85
1.05 0.0335 0.0413
H 0.013 0.100 0.0005 0.0040
J
0.10
0.26 0.0040 0.0102
K
0.20
0.60 0.0079 0.0236
L
1.25
1.55 0.0493 0.0610
M
0_
10 _
0_
10 _
S
2.50
3.00 0.0985 0.1181
G
A
J
C
0.05 (0.002)
H
M
K
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm
inches
THIN SOT23−5/TSOP−5/SC59−5
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHC1GT04/D