ON Semiconductort
Octal Bus Buffer/Line Driver
MC74VHC240
Inverting with 3−State Outputs
The MC74VHC240 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC240 is an inverting 3−state buffer, and has two
active−low output enables. This device is designed to drive bus lines
or buffer memory address registers.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
• High Speed: tPD = 3.6ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.9V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 120 FETs or 30 Equivalent Gates
w
DW SUFFIX
20−LEAD SOIC WIDE PACKAGE
CASE 751D−05
DT SUFFIX
20−LEAD TSSOP PACKAGE
CASE 948E−02
M SUFFIX
20−LEAD SOIC EIAJ PACKAGE
CASE 967−01
ORDERING INFORMATION
MC74VHCXXXDW
SOIC WIDE
MC74VHCXXXDT
TSSOP
MC74VHCXXXM
SOIC EIAJ
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
OEA
1
20
VCC
A1
2
19
OEB
YB4
3
18
YA1
A2
4
17
B4
YB3
5
16
YA2
A3
6
15
B3
YB2
7
14
YA3
A4
8
13
B2
YB1
9
12
YA4
GND
10
11
B1
PIN ASSIGNMENT
FUNCTION TABLE
INPUTS
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 4
1
OUTPUTS
OEA, OEB
A, B
YA, YB
L
L
H
L
H
X
H
L
Z
Publication Order Number:
MC74VHC240/D
A1
A2
A3
DATA
INPUTS
A4
B1
B2
B3
B4
OUTPUT
ENABLES
2
18
4
16
6
14
8
12
11
9
13
7
15
5
17
3
YA1
YA2
YA3
YA4
YB1
INVERTING
OUTPUTS
YB2
YB3
YB4
1
OEA
19
OEB
Figure 1. LOGIC DIAGRAM
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MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
− 40
+ 85
_C
0
0
100
20
ns/V
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
VCC = 3.3V ±0.3V
VCC =5.0V ±0.5V
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2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
VIH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = − 50μA
Vin = VIH or VIL
IOH = − 4mA
IOH = − 8mA
VOL
Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50μA
TA = 25°C
Min
Max
1.50
VCC x 0.7
Min
2.0
3.0
4.5
1.9
2.9
4.4
3.0
4.5
2.58
3.94
Max
1.50
VCC x 0.7
0.50
VCC x 0.3
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4mA
IOL = 8mA
Typ
TA = − 40 to 85°C
2.0
3.0
4.5
Unit
V
0.50
VCC x 0.3
V
V
1.9
2.9
4.4
2.48
3.80
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
V
Iin
Maximum Input
Leakage Current
Vin = 5.5V or GND
0 to 5.5
± 0.1
± 1.0
μA
IOZ
Maximum
Three−State Leakage
Current
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.25
± 2.5
μA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
4.0
40.0
μA
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3
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
tPLH,
tPHL
Maximum Propagation Delay,
A to YA or B to YB
tPZL,
tPZH
tPLZ,
tPHZ
tOSLH,
tOSHL
Output Enable Time
OEA to YA or OEB to YB
Output Disable Time
OEA to YA or OEB to YB
Output to Output Skew
Test Conditions
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
5.3
7.8
7.5
11.0
1.0
1.0
9.0
12.5
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
3.6
5.1
5.5
7.5
1.0
1.0
6.5
8.5
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 15pF
CL = 50pF
6.6
9.1
10.6
14.1
1.0
1.0
12.5
16.0
VCC = 5.0 ± 0.5V
RL = 1kΩ
CL = 15pF
CL = 50pF
4.7
6.2
7.3
9.3
1.0
1.0
8.5
10.5
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 50pF
10.3
14.0
1.0
16.0
VCC = 5.0 ± 0.5V
RL = 1kΩ
CL = 50pF
6.7
9.2
1.0
10.5
VCC = 3.3 ± 0.3V
(Note 1.)
CL = 50pF
1.5
1.5
VCC = 5.0 ± 0.5V
(Note 1.)
CL = 50pF
1.0
1.0
10
10
Cin
Maximum Input Capacitance
4
Cout
Maximum Three−State Output
Capacitance (Output in
High−Impedance State)
6
ns
ns
ns
pF
pF
Typical @ 25°C, VCC = 5.0V
CPD
17
Power Dissipation Capacitance (Note 2.)
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Typ
Parameter
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.6
0.9
V
VOLV
Quiet Output Minimum Dynamic VOL
− 0.6
− 0.9
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
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4
SWITCHING WAVEFORMS
A or B
VCC
50%
tPHL
YA or YB
tPLH
OEA or OEB
VCC
50%
GND
tPZL
50% VCC
YA or YB
50% VCC
tPZH
YA or YB
tPHZ
50% VCC
Figure 2.
GND
tPLZ
HIGH
IMPEDANCE
VOL +0.3V
VOH −0.3V
HIGH
IMPEDANCE
Figure 3.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 4. Test Circuit
Figure 5. Test Circuit
INPUT
Figure 6. Input Equivalent Circuit
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5
OUTLINE DIMENSIONS
DW SUFFIX
SOIC
CASE 751D−05
ISSUE F
A
20
q
X 45 _
E
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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6
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
OUTLINE DIMENSIONS
DT SUFFIX
TSSOP
CASE 948E−02
ISSUE A
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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7
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
1.20
−−−
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
0.047
−−−
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
OUTLINE DIMENSIONS
M SUFFIX
SOIC EIAJ
CASE 967−01
ISSUE O
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−−
0.032
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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MC74VHC240/D
