MC74VHC373MELG

MC74VHC373 Octal D-Type Latch with 3-State Output The MC74VHC373 is an advanced high speed CMOS octal latch with 3−state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8−bit D−type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. http://onsemi.com MARKING DIAGRAM 20 20 1 SOIC−20 DW SUFFIX CASE 751D 1 Features • • • • • • • • • • • • VHC373 AWLYYWWG High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.9 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 186 FETs or 46.5 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant VHC373 A WL, L Y WW, W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 10 11 LE GND ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 8 1 Publication Order Number: MC74VHC373/D MC74VHC373 D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LE OE 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 Q0 Q1 FUNCTION TABLE Q2 Q3 Q4 INPUTS NONINVERTING OUTPUTS Q5 Q6 Q7 OUTPUT OE LE D Q L L L H H H L X H L X X H L No Change Z 11 1 Figure 1. Logic Diagram MAXIMUM RATINGS Symbol Parameter VCC DC Supply Voltage Value Unit – 0.5 to + 7.0 V Vin DC Input Voltage – 0.5 to + 7.0 V Vout DC Output Voltage – 0.5 to VCC + 0.5 V IIK Input Diode Current − 20 mA IOK Output Diode Current ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, 500 mW Tstg Storage Temperature – 65 to + 150 _C SOIC Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 5.5 V VCC DC Supply Voltage Vin DC Input Voltage 0 5.5 V Vout DC Output Voltage 0 VCC V − 40 + 85 _C 0 0 100 20 ns/V TA Operating Temperature tr, tf Input Rise and Fall Time VCC = 3.3 V VCC = 5.0 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 2 MC74VHC373 DC ELECTRICAL CHARACTERISTICS Symbol Parameter VCC V Test Conditions VIH Minimum High−Level Input Voltage 2.0 3.0 to 5.5 VIL Maximum Low−Level Input Voltage 2.0 3.0 to 5.5 VOH Minimum High−Level Output Voltage Vin = VIH or VIL IOH = − 50 mA Vin = VIH or VIL IOH = − 4 mA IOH = − 8 mA VOL Maximum Low−Level Output Voltage Vin = VIH or VIL IOL = 50 mA TA = 25°C Min Typ Max Min 1.50 VCC x 0.7 2.0 3.0 4.5 1.9 2.9 4.4 3.0 4.5 2.58 3.94 Max 1.50 VCC x 0.7 0.50 VCC x 0.3 2.0 3.0 4.5 Unit V 0.50 VCC x 0.3 V V 1.9 2.9 4.4 2.48 3.80 2.0 3.0 4.5 Vin = VIH or VIL IOL = 4 mA IOL = 8 mA TA = − 40 to 85°C 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 V Iin Maximum Input Leakage Current Vin = 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0 mA IOZ Maximum Three−State Leakage Current Vin = VIL or VIH Vout = VCC or GND 5.5 ± 0.25 ± 2.5 mA ICC Maximum Quiescent Supply Current Vin = VCC or GND 5.5 4.0 40.0 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Symbol Parameter tPLH, tPHL Maximum Propagation Delay, D to Q tPLH, tPHL tPZL, tPZH tPLZ, tPHZ tOSLH, tOSHL Maximum Propagation Delay, LE to Q Output Enable Time, OE to Q Output Disable Time, OE to Q Output to Output Skew Test Conditions Min TA = − 40 to 85°C Typ Max Min Max Unit ns VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 7.3 9.8 11.4 14.9 1.0 1.0 13.5 17.0 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 4.9 6.4 7.2 9.2 1.0 1.0 8.5 10.5 VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 7.0 9.5 11.0 14.5 1.0 1.0 13.0 16.5 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 5.0 6.5 7.2 9.2 1.0 1.0 8.5 10.5 VCC = 3.3 ± 0.3 V RL = 1 kW CL = 15 pF CL = 50 pF 7.3 9.8 11.4 14.9 1.0 1.0 13.5 17.0 VCC = 5.0 ± 0.5 V RL = 1 kW CL = 15 pF CL = 50 pF 5.5 7.0 8.1 10.1 1.0 1.0 9.5 11.5 VCC = 3.3 ± 0.3 V RL = 1 kW CL = 50 pF 9.5 13.2 1.0 15.0 VCC = 5.0 ± 0.5V RL = 1 kW CL = 50 pF 6.5 9.2 1.0 10.5 VCC = 3.3 ± 0.3 V (Note 1) CL = 50 pF 1.5 1.5 ns VCC = 5.5 ± 0.5 V (Note 1) CL = 50 pF 1.0 1.0 ns http://onsemi.com 3 ns ns ns MC74VHC373 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Symbol Parameter Test Conditions Min TA = − 40 to 85°C Typ Max 10 Cin Maximum Input Capacitance 4 Cout Maximum Three−State Output Capacitance (Output in High−Impedance State) 6 Min Max Unit 10 pF pF Typical @ 25°C, VCC = 5.0 V CPD 27 Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 8 (per latch). CPD is used to determine the no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V) TA = 25°C Symbol Parameter Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.6 0.9 V VOLV Quiet Output Minimum Dynamic VOL − 0.6 − 0.9 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V TIMING REQUIREMENTS (Input tr = tf = 3.0 ns) TA = − 40 to 85°C TA = 25°C Symbol Parameter Test Conditions Typ Limit Limit Unit Minimum Pulse Width, LE VCC = 3.3 ± 0.3 V VCC = 5.0 ±0.5 V 5.0 5.0 5.0 5.0 ns tsu Minimum Setup Time, D to LE VCC = 3.3 ± 0.3 V VCC = 5.0 ± 0.5 V 4.0 4.0 4.0 4.0 ns th Minimum Hold Time, D to LE VCC = 3.3 ± 0.3 V VCC = 5.0 ± 0.5 V 1.0 1.0 1.0 1.0 ns tw(h) ORDERING INFORMATION Device MC74VHC373DWR2G Package Shipping† SOIC−20 (Pb−Free) 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74VHC373 SWITCHING WAVEFORMS tw VCC D LE 50% VCC 50% GND GND tPHL tPLH tPHL tPLH 50% VCC Q Q 50% VCC Figure 2. Figure 3. VCC OE 50% GND tPZL tPLZ 50% VCC Q VALID VCC HIGH IMPEDANCE D 50% tsu VOL +0.3V tPZH tPHZ 50% VCC Q VCC LE VOL -0.3V GND th 50% GND HIGH IMPEDANCE Figure 4. Figure 5. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 6. Figure 7. http://onsemi.com 5 MC74VHC373 D0 3 D1 4 D Q D LE LE OE D2 7 Q D3 8 D LE Q D4 13 D LE Q D5 14 D LE Q D6 17 D LE Q D7 18 D LE Q D LE Q LE 11 1 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 Figure 8. EXPANDED LOGIC DIAGRAM INPUT Figure 9. INPUT EQUIVALENT CIRCUIT http://onsemi.com 6 15 Q5 16 Q6 19 Q7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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