MC74VHC74DTR2

MC74VHC74 Dual D-Type Flip-Flop with Set and Reset The MC74VHC74 is an advanced high speed CMOS D−type flip−flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. www.onsemi.com MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 14 1 VHC74G AWLYWW 1 14 Features • • • • • • • • • • • • • High Speed: fmax = 170MHz (Typ) at VCC = 5V Low Power Dissipation: ICC = 2mA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 128 FETs or 32 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant RD1 D1 CP1 SD1 1 RD2 2 5 3 6 Q1 D2 Q1 CP2 4 SD2 9 11 8 1 A = Assembly Location WL, L = Wafer Lot Y, YY = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs Outputs SD RD CP D L H L H H H H H H L L H H H H H X X X X X X H L X X X L H Q Q H L L H H* H* H L L H No Change No Change No Change Q2 Q2 10 1 *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. 13 12 VHC 74 ALYWG G TSSOP−14 DT SUFFIX CASE 948G ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Figure 1. LOGIC DIAGRAM © Semiconductor Components Industries, LLC, 2011 April, 2019 − Rev. 9 1 Publication Order Number: MC74VHC74/D MC74VHC74 RD1 1 14 VCC D1 2 13 RD2 CP1 3 12 D2 SD1 4 11 CP2 Q1 5 10 SD2 Q1 6 9 Q2 GND 7 8 Q2 Figure 2. PIN ASSIGNMENT MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage – 0.5 to + 7.0 V Vin DC Input Voltage – 0.5 to + 7.0 V Vout DC Output Voltage – 0.5 to VCC + 0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature –65 to +150 _C SOIC Packages† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating SOIC Packages: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 5.5 V VCC DC Supply Voltage Vin DC Input Voltage 0 5.5 V Vout DC Output Voltage 0 VCC V −55 + 125 _C 0 0 100 20 ns/V TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time VCC = 3.3V ±0.3V VCC =5.0V ±0.5V www.onsemi.com 2 MC74VHC74 DC ELECTRICAL CHARACTERISTICS Min 1.50 VCC x 0.7 Symbol Parameter VIH Minimum High−Level Input Voltage 2.0 3.0 to 5.5 VIL Maximum Low−Level Input Voltage 2.0 3.0 to 5.5 VOH Minimum High−Level Output Voltage VOL Maximum Low−Level Output Voltage Test Conditions TA = 25°C VCC V TA = −55°C to +125°C Typ Max Min 1.50 VCC x 0.7 0.50 VCC x 0.3 Vin = VIH or VIL IOH = − 50mA 2.0 3.0 4.5 1.9 2.9 4.4 Vin = VIH or VIL IOH = − 4mA IOH = − 8mA 3.0 4.5 2.58 3.94 Vin = VIH or VIL IOL = 50mA 2.0 3.0 4.5 Vin = VIH or VIL IOL = 4mA IOL = 8mA Max V 0.50 VCC x 0.3 2.0 3.0 4.5 Unit V V 1.9 2.9 4.4 2.48 3.80 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 V Iin Maximum Input Leakage Current Vin = 5.5V or GND 0 to 5.5 ± 0.1 ± 1.0 mA ICC Maximum Quiescent Supply Current Vin = VCC or GND 5.5 2.0 20.0 mA AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Symbol tPLH, tPHL tPLH, tPHL fmax Cin Parameter Maximum Propagation Delay, CP to Q or Q Maximum Propagation Delay, SD or RD to Q or Q Maximum Clock Frequency (50% Duty Cycle) Test Conditions Min TA = −55°C to +125°C Typ Max Min Max Unit ns VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 6.7 9.2 11.9 15.4 1.0 1.0 14.0 17.5 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 4.6 6.1 7.3 9.3 1.0 1.0 8.5 10.5 VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 7.6 10.1 12.3 15.8 1.0 1.0 14.5 18.0 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 4.8 6.3 7.7 9.7 1.0 1.0 9.0 11.0 VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 80 50 125 75 70 45 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 130 90 170 115 110 75 Maximum Input Capacitance 4 10 ns MHz 10 pF Typical @ 25°C, VCC = 5.0V CPD 25 Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 2 (per flip−flop). CPD is used to determine the no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC. www.onsemi.com 3 MC74VHC74 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (Input tr = tf = 3.0ns) Symbol Parameter Guaranteed Limit VCC V TA = 25_C TA = −55°C to +125°C Unit tw Minimum Pulse Width, CP 3.3 ± 0.3 5.0 ± 0.5 6.0 5.0 7.0 5.0 ns tw Minimum Pulse Width, RD or SD 3.3 ± 0.3 5.0 ± 0.5 6.0 5.0 7.0 5.0 ns tsu Minimum Setup Time, D to CP 3.3 ± 0.3 5.0 ± 0.5 6.0 5.0 7.0 5.0 ns th Minimum Hold Time, D to CP 3.3 ± 0.3 5.0 ± 0.5 0.5 0.5 0.5 0.5 ns Minimum Recovery Time, SD or RD to CP 3.3 ± 0.3 5.0 ± 0.5 5.0 3.0 5.0 3.0 ns trec ORDERING INFORMATION Package Shipping† MC74VHC74DR2G SOIC−14 (Pb−Free) 2500 / Tape & Reel MC74VHC74DTG TSSOP−14 (Pb−Free) 96 Units / Rail MC74VHC74DTR2G TSSOP−14 (Pb−Free) 2500 / Tape & Reel NLV74VHC74DTR2G* TSSOP−14 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 4 MC74VHC74 tw SD or RD GND VCC CP tPHL 50% GND Q or Q tw 1/fmax tPLH VCC 50% 50% VCC tPLH tPHL Q or Q 50% VCC 50% VCC trec Q or Q VCC 50% CP Figure 3. GND Figure 4. Switching Waveforms TEST POINT VALID OUTPUT VCC D 50% DEVICE UNDER TEST GND tsu th CL* VCC 50% CP GND *Includes all probe and jig capacitance Figure 5. Figure 6. INPUT Figure 7. Input Equivalent Circuit www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G ISSUE C 14 DATE 17 FEB 2016 1 SCALE 2:1 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− K1 J J1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX ALYWG G 7.06 1 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: 98ASH70246A DESCRIPTION: TSSOP−14 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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