MC75172B, MC75174B
Quad EIA−485 Line Drivers
with Three−State Outputs
The ON Semiconductor MC75172B/174B Quad Line drivers are
differential high speed drivers designed to comply with the EIA−485
Standard. Features include three−state outputs, thermal shutdown, and
output current limiting in both directions. These devices also comply
with EIA−422−A, and CCITT Recommendations V.11 and X.27.
The MC75172B/174B are optimized for balanced multipoint bus
transmission at rates in excess of 10 MBPS. The outputs feature wide
common mode voltage range, making them suitable for party line
applications in noisy environments. The current limit and thermal
shutdown features protect the devices from line fault conditions.
These devices offer optimum performance when used with the
MC75173 and MC75175 line receivers.
Both devices are available in 16−pin plastic PDIP and 20−pin wide
body surface mount packages.
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QUAD EIA−485 LINE DRIVERS
SOIC−20 WB
DW SUFFIX
CASE 751D
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
Meets EIA−485 Standard for Party Line Operation
Meets EIA−422−A and CCITT Recommendations V.11 and X.27
Operating Ambient Temperature: −40°C to +85°C
High Impedance Outputs
Common Mode Output Voltage Range: −7.0 to 12 V
Positive and Negative Current Limiting
Transmission Rates in Excess of 10 MBPS
Thermal Shutdown at 150°C Junction Temperature, (± 20°C)
Single 5.0 V Supply
Pin Compatible with TI SN75172/4 and NS mA96172/4
Interchangeable with MC3487 and AM26LS31 for EIA−422−A
Applications
Pb−Free Packages are Available*
PDIP−16
P SUFFIX
CASE 648
1
MARKING DIAGRAMS
20
MC17517xBDW
AWLYYWWG
MAXIMUM RATING
Rating
1
Symbol
Value
Unit
Power Supply Voltage
VCC
−0.5, +7.0
Vdc
Input Voltage (Data, Enable)
Vin
+7.0
Vdc
Input Current (Data, Enable)
Iin
−24
mA
Applied Output Voltage, when in 3−State
Condition (VCC = 5.0 V)
Vza
−10, +14
Vdc
Applied Output Voltage, when VCC = 0 V
Vzb
±14
Vdc
IO
Self−Limiting
−
Tstg
−65, +150
°C
Output Current
Storage Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Devices should not be operated at these limits. The “Recommended Operating
Conditions” table provides for actual device operation.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 4
1
16
MC75174BP
AWLYYWWG
1
x
A
WL
YY
WW
G
= 2 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Publication Order Number:
MC75172B/D
MC75172B, MC75174B
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VCC
+4.75
+5.0
+5.25
Vdc
Input Voltage (All Inputs)
Vin
0
−
VCC
Vdc
Output Voltage in 3−State Condition, or when VCC = 0 V
Vcm
−7.0
−
+12
Vdc
Output Current (Normal data transmission)
IO
−65
−
+65
mA
Operating Ambient Temperature (see text)
EIA−485
EIA−422
TA
−
+85
°C
Unit
−40
0
2. All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (−40°C p TA p 85°C, 4.75 V p VCC p 5.25 V, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
VO
VOH
VOL
0
−
−
−
4.0
1.6
6.0
−
−
⎥ VOD1 ⎜
⎥ VOD2 ⎜
1.5
1.5
3.4
2.3
6.0
5.0
⎥ DVOD2 ⎜
⎥ VOD2A ⎜
⎥ DVOD2A ⎜
⎥ VOD3 ⎜
⎥ DVOD3 ⎜
VOS
⎥ DVOS ⎜
−
−
−
1.5
−
−
−
5.0
2.2
5.0
−
5.0
2.9
5.0
200
−
200
5.0
200
−
200
mVdc
Vdc
mVdc
Vdc
mVdc
Vdc
mVdc
IO(off)
IOZ
−50
−50
0
0
+50
+50
mA
IOSR
IOS
−150
−250
−
−
+150
+250
mA
VIL(A)
VIL(B)
VIH
0
0
2.0
−
−
−
0.7
0.8
VCC
Current @ Vin = 2.7 V (All Inputs)
Current @ Vin = 0.5 V (All Inputs)
IIH
IIL
−
−100
0.2
−15
20
−
mA
Clamp Voltage (All Inputs, Iin = −18 mA)
VIK
−1.5
−
−
Vdc
Thermal Shutdown Junction Temperature
Tjts
−
+150
−
°C
Power Supply Current (Outputs Open, VCC = 5.25 V)
Outputs Enable
Outputs Disabled
ICC
−
−
60
30
70
40
Output Voltage
Single−Ended Voltage
IO = 0
High @ IO = −33 mA
Low @ IO = +33 mA
Differential Voltage
Open Circuit (IO = 0)
RL = 54 W (Figure 1)
Vdc
Change in Differential*, RL = 54 W (Figure 1)
Differential Voltage, RL = 100 W (Figure 1)
Change in Differential*, RL = 100 W (Figure 1)
Differential Voltage, −7.0 V p Vcm p 12 V (Figure 2)
Change in Differential*, −7.0 V p Vcm p 12 V (Figure 2)
Offset Voltage, RL = 54 W (Figure 1)
Change in Offset*, RL = 54 W (Figure 1)
Output Current (Each Output)
Power Off Leakage, VCC = 0, −7.0 V p VO p 12 V
Leakage in 3−State Mode, −7.0 V p VO p 12 V
Short Circuit Current to Ground
Short Circuit Current, −7.0 V p VO p 12 V
Inputs
Low Level Voltage (Pins 4 & 12, MC75174B only)
Low Level Voltage (All Other Pins)
High Level Voltage (All Inputs)
Vdc
3. *Vin switched from 0.8 to 2.0 V. Typical values determined at 25°C ambient and 5.0 V supply.
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2
mA
MC75172B, MC75174B
TIMING CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Characteristics
Symbol
Min
Typ
Max
tPLH
tPHL
−
−
23
18
30
30
Propagation Delay − Input to Differential Output (Figure 4)
Input Low−to−High
Input High−to−Low
tPLH(D)
tPHL(D)
−
−
15
17
25
25
Differential Output Transition Time (Figure 4)
tdr, tdf
−
19
25
tSK1
tSK2
tSK3
−
−
−
0.2
1.5
1.5
−
−
−
Propagation Delay − Input to Single−ended Output (Figure 3)
Output Low−to−High
Output High−to−Low
Unit
ns
ns
Skew Timing
⎜tPLHD − tPHLD ⎜ for Each Driver
Max − Min tPLHD Within a Package
Max − Min tPHLD Within a Package
ns
ns
Enable Timing
Single−ended Outputs (Figure 5)
Enable to Active High Output
Enable to Active Low Output
Active High to Disable (using Enable)
Active Low to Disable (using Enable)
Enable to Active High Output (MC75172B only)
Enable to Active Low Output (MC75172B only)
Active High to Disable (using Enable, MC75172B only)
Active Low to Disable (using Enable, MC75172B only)
ns
Differential Outputs (Figure 6)
Enable to Active Output
Enable to Active Output (MC75172B only)
Enable to 3−State Output
Enable to 3−State Output (MC75172B only)
tPZH(E)
tPZL(E)
tPHZ(E)
tPLZ(E)
tPZH(E)
tPZL(E)
tPHZ(E)
tPLZ(E)
−
−
−
−
−
−
−
−
48
20
35
30
58
28
38
36
60
30
45
50
70
35
50
50
tPZD(E)
tPZD(E)
tPDZ(E)
tPDZ(E)
−
−
−
−
47
56
32
40
−
−
−
−
ns
PIN CONNECTIONS
MC75172B
MC75174B
1A 1
20 VCC
1A 1
16 VCC
1A 1
20 VCC
1Y 2
19 4A
1Y 2
15 4A
1Y 2
19 4A
NC 3
18 4Y
1Z 3
14 4Y
NC 3
18 4Y
1Z 4
17 NC
13 4Z
1Z 4
17 NC
En 5
16 4Z
En 4
12
2Z 5
15 En
2Y 6
En 5
12
2Z 6
16 4Z
2Z 6
12 En
34
11 3Z
NC 7
14 3Z
2A 7
10 3Y
NC 7
15 En
34
14 3Z
2Y 8
13 NC
GND 8
9 3A
2Y 8
13 NC
2A 9
12 3Y
2A 9
12 3Y
GND 10
11 3A
GND 10
11 3A
P Package
DW Package
DW Package
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3
MC75172B, MC75174B
VCC
VCC
375
RL/2
Vin
(0.8 or 2.0 V)
Vin
(0.8 or 2.0 V)
VOD2,A
RL/2
VOD3
58
+
VCM = 12 to −7.0 V
375
VOS
Figure 1. VDD Measurement
Figure 2. Common Mode Test
3.0 V
VCC
1.5 V
0V
tPLH
tPHL
27 W
Y
Vin
Vin
2.3 V
1.5 V
Output
Z
15 pF
3.0 V
3.0 V
Output Y
VOL
S.G.
tPLH
Output Z
tPHL
VOH
3.0 V
3.0 V
Figure 3. Propagation Delay, Single−Ended Outputs
3.0 V
VCC
Vin
Vin
S.G.
NOTES:
54
50 pF
1.5 V
1.5 V
0V
tPLHD
VOD
VOD
1.5 V
50%
−1.5 V
tPHLD
tdr
1.S.G. set to: f p 1.0 MHz; duty cycle = 50%; tr, tf, p 5.0 ns.
2.tSK1 = ⎥ tPLHD − tPHLD⎥ for each driver.
3.tSK2 computed by subtracting the shortest tPLHD from the longest tPLHD of the 4 drivers within a package.
4.tSK3 computed by subtracting the shortest tPHLD from the longest tPHLD of the 4 drivers within a package.
Figure 4. Propagation Delay, Differential Outputs
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4
1.5 V
50%
−1.5 V
[4.6 V
tdf
MC75172B, MC75174B
3.0 V
VCC
0 or 3.0 V
Vin
1.5 V
1.5 V
Vin
0V
tPZH(E)
Vout
110W
tPHZ(E)
50 pF
3.0 V
VOH
0.5 V
2.3 V
Vout
S.G.
VCC
VCC
3.0 V
110W
0 or 3.0 V
1.5 V
1.5 V
Vin
0V
tPZL(E)
Vout
tPLZ(E)
50 pF
Vin
3.0 V
Vout
2.3 V
0.5 V
S.G.
VOL
Figure 5. Enable Timing, Single−Ended Outputs
3.0 V
VCC
1.5 V
Vin
0 or 3.0 V
Vin
54
50 pF
1.5 V
0V
tPZD(E)
VOD
tPDZ(E)
3.0 V
1.5 V
VOD
1.5 V
0
S.G.
NOTES:
0
Disabled
1.S.G. set to: f p 1.0 MHz; duty cycle = 50%; tf, tf, p 5.0 ns.
2.Vin is inverted for Enable measurements.
Figure 6. Enable Timing, Differential Outputs
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5
Active
Disabled
MC75172B, MC75174B
2.0
VOL, OUTPUT VOLTAGE (V)
VOL, OUTPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
IOL = 27.8 mA
1.75
IOL = 20.0 mA
1.5
1.25
4.75 V p VCC p 5.25 V
4.75V p VCC p5.25 V
TA = 25°C
0
0
10
20
30
40
50
IOL, OUTPUT CURRENT (mA)
60
1.0
− 40
70
Figure 7. Single−Ended Output Voltage
versus Output Sink Current
VCC = 5.25 V
4.0
VCC = 5.00 V
4.0
VCC = 4.75 V
3.0
2.0
TA = 25°C
1.0
0
− 10
− 20
− 30
− 40
− 50
IOH, OUTPUT CURRENT (mA)
− 60
3.5
VCC = 4.75 V
− 70
− 40
VOD , DIFFERENTIAL OUTPUT VOLTAGE (V)
VOD , DIFFERENTIAL OUTPUT VOLTAGE (V)
VCC = 5.25 V
VCC = 5.0 V
VCC = 4.75 V
1.0
VOD
TA = 25°C
0
0
10
20
30
40
50
IO, OUTPUT CURRENT (mA)
60
− 20
0
40
60
20
TA, AMBIENT TEMPERATURE (°C)
85
Figure 10. Single−Ended Output
Voltage versus Temperature
3.0
IO
IOH = −27.8 mA
3.25
4.0
0.8 or
2.0 V
85
IOH = −20.0 mA
3.75
Figure 9. Single−Ended Output Voltage
versus Output Source Current
2.0
0
20
40
60
TA, AMBIENT TEMPERATURE (°C)
Figure 8. Single−Ended Output Voltage
versus Temperature
VOH, OUTPUT VOLTAGE (V)
VOH, OUTPUT VOLTAGE (V)
5.0
− 20
70
4.0
3.0
IO = 20.0 mA
IO = 27.8 mA
2.0
1.0
0.8 or
2.0 V
0
−40
Figure 11. Output Differential Voltage
versus Load Current
−20
IO
VOD
VCC = 4.75 V
0
20
40
60
TA, AMBIENT TEMPERATURE (°C)
Figure 12. Output Differential Voltage
versus Temperature
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6
85
MC75172B, MC75174B
20
IOX, IOZ, LEAKAGE CURRENT (μ A)
IOZ, LEAKAGE CURRENT (μ A)
2.0
1.0
0
15
10
5.0
Vout = 7.0 V
−5.0
−1.0
TA = 25°C
En = Low, En = High
−2.0
−7.0
−3.0
1.0
5.0
9.0
Vz, APPLIED OUTPUT VOLTAGE (V)
−10
−20
−40
12
−20
0
20
40
TA, AMBIENT TEMPERATURE (°C)
60
85
Figure 14. Output Leakage Current
versus Temperature
150
IOS , SHORT CIRCUIT CURRENT (mA)
5.0
0
Enable
Pins
− 5.0
Driver
Inputs
− 10
− 15
4.75 p VCC p 5.25 V
TA = 25°C
− 20
− 25
− 0.5
En = Low, En = High
or VCC = 0 V
−15
Figure 13. Output Leakage Current
versus Output Voltage
I in , INPUT CURRENT (μ A)
Vout = +12 V
0
0.5
1.5
2.5
3.5
Vin, INPUT VOLTAGE (V)
4.5
5.5
Normally Low Output
90
30
0
Normally High Output
− 30
−9
0
−150
−7.0
Figure 15. Input Current
versus Input Voltage
TA = 25°C
4.75 p VCC p 5.25 V
−3.0
1.0
5.0
9.0
Vz, APPLIED OUTPUT VOLTAGE (V)
Figure 16. Short Circuit Current
versus Common Mode Voltage
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7
12
MC75172B, MC75174B
APPLICATIONS INFORMATION
Description
The MC75172B and MC75174B are differential line
drivers designed to comply with EIA−485 Standard (April
1983) for use in balanced digital multipoint systems
containing multiple drivers. The drivers also comply with
EIA−422−A and CCITT Recommendations V.11 and X.27.
The drivers meet the EIA−485 requirement for protection
from damage in the event that two or more drivers attempt
to transmit data simultaneously on the same cable. Data
rates in excess of 10 MBPS are possible, depending on the
cable length and cable characteristics. A single power
supply, 5.0 V, ±5%, is required at a nominal current of
60 mA, plus load currents.
The drivers are protected from short circuits by two
methods:
a) Current limiting is provided at each output, in both
the source and sink direction, for shorts to any
voltage within the range of 12V to −7.0V, with
respect to circuit ground (see Figure 16). The short
circuit current will flow until the fault is removed, or
until the thermal shutdown circuit activates (see
below). The current limiting circuit has a negative
temperature coefficient and requires no resetting
upon removal of the fault condition.
b) A thermal shutdown circuit disables the outputs
when the junction temperature reaches 150°C,
± 20°C. The thermal shutdown circuit has a
hysteresis of ≈ 12°C to prevent oscillations. When
this circuit activates, the output stage of each driver
is put into the high impedance mode, thereby
shutting off the output currents. The remainder of the
internal circuitry remains biased. The outputs will
become active once again as the IC cools down.
Outputs
Each output (when active) will be a low or a high voltage,
which depends on the input state and the load current (see
Table 1, 2 and Figures 7 to 10). The graphs apply to each
driver, regardless of how many other drivers within the
package are supplying load current.
Table 1. MC75172B Truth Table
Enables
Outputs
Data Input
EN
EN
Y
Z
Driver Inputs
H
L
H
L
X
H
H
X
X
L
X
X
L
L
H
H
L
H
L
Z
L
H
L
H
Z
The driver inputs determine the state of the outputs in
accordance with Tables 1 and 2. The driver inputs have a
nominal threshold of 1.2 V, and their voltage must be kept
within the range of 0 V to VCC for proper operation. If the
voltage is taken more than 0.5 V below ground, excessive
currents will flow, and proper operation of the drivers will
be affected. An open pin is equivalent to a logic high, but
good design practices dictate that inputs should never be
left open. The characteristics of the driver inputs are shown
in Figure 15. This graph is not affected by the state of the
Enable pins.
Table 2. MC75174B Truth Table
Outputs
Data Input
Enable
Y
H
L
X
H
H
L
H
L
Z
Z
L
H
Z
H = Logic high, L = Logic low, X = Irrelevant, Z = High impedance
Enable Logic
Each driver’s outputs are active when the Enable inputs
(Pins 4 and 12) are true according to Tables 1 and 2.
The Enable inputs have a nominal threshold of 1.2 V and
their voltage must be kept within the range of 0 V to VCC
for proper operation. If the voltage is taken more than 0.5 V
below ground, excessive currents will flow, and proper
operation of the drivers will be affected. An open pin is
equivalent to a logic high, but good design practices dictate
that inputs should never be left open. The Enable input
characteristics are shown in Figure 15.
The two outputs of a driver are always complementary.
A “high” output can only source current out, while a “low”
output can only sink current (except for short circuit current
− see Figure 16).
The outputs will be in the high impedance mode when:
a) the Enable inputs are set according to Table 1 or 2;
b) VCC is less than 1.5 V;
c) the junction temperature exceeds the trip point of
the thermal shutdown circuit (see below). When in
this condition, the output’s source and sink
capability are shut off, and only leakage currents
will flow (see Figures 13, 14). Disabled outputs may
be taken to any voltage between −7.0 V and 12 V
without damage.
Operating Temperature Range
The minimum ambient operating temperature is listed as
−40°C to meet EIA−485 specifications, and 0°C to meet
EIA−422−A specifications. The higher VOD required by
EIA−422−A is the reason for the narrower temperature range.
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8
MC75172B, MC75174B
drivers. From Figures 8 and 10 (adjusted for VCC = 5.0 V),
VOL [1.38 V, and VOH [4.27 V. The power dissipated
in each driver is:
{(5.0 − 4.27) • 0.020} + (1.38 • 0.0278) = 53 mW
Since each driver dissipates 53 mW, the use of all four
drivers in a package would be marginal. Options include
reducing the load current, reducing the ambient
temperature, and/or providing a heat sink.
The maximum ambient operating temperature
(applicable to both EIA−485 and EIA−422−A) is listed as
85°C. However, a lower ambient may be required
depending on system use (i.e. specifically how many
drivers within a package are used) and at what current
levels they are operating. The maximum power which may
be dissipated within the package is determined by:
PDmax +
where:
T
–T
Jmax A
R
qJA
System Requirements
EIA−485 requires each driver to be capable of
transmitting data differentially to at least 32 unit loads, plus
an equivalent DC termination resistance of 60W, over a
common mode voltage of −7.0 to 12 V. A unit load (U.L.),
as defined by EIA−485, is shown in Figure 17.
RqJA = package thermal resistance (typical
70°C/W for the DIP package, 85°C/W for
SOIC package);
TJmax = max. operating junction
temperature, and
TA = ambient temperature.
I
1.0 mA
Since the thermal shutdown feature has a trip point of
150°C, ±20°C, TJmax is selected to be 130°C. The power
dissipated within the package is calculated from:
PD
where:
−7.0 V
= {[(VCC − VOH) • IOH] + VOL • IOL)} each
driver = + (VCC • ICC)
VCC = the supply voltage;
VOH, VOL are measured or estimated from
Figures 7 to 10;
ICC = the quiescent power supply current
(typical 60 mA).
V
5.0 V
12 V
−0.8 mA
Reprinted from EIA−485, Electronic Industries Association,
Washington,DC.
Figure 17. Unit Load Definition
As indicated in the equation, the first term (in brackets)
must be calculated and summed for each of the four drivers,
while the last term is common to the entire package.
Example 1: TA = 25°C, IOL = IOH = 55 mA for each
driver, VCC = 5.0 V, DIP package. How many drivers per
package can be used?
Maximum allowable power dissipation is:
PD max +
−3.0 V
A load current within the shaded regions represents an
impedance of less than one U.L., while a load current of a
magnitude outside the shaded area is greater than one U.L.
A system’s total load is the sum of the unit load equivalents
of each receiver’s input current, and each disabled driver’s
output leakage current. The 60W termination resistance
mentioned above allows for two 120W terminating
resistors.
Using the EIA−485 requirements (worst case limits), and
the graphs of Figures 7 and 9, it can be determined that the
maximum current an MC75172B or MC75174B driver will
source or sink is [65 mA.
130°C * 25°C
+ 1.5 W
70°CńW
Since the power supply current of 60 mA dissipates
300 mW, that leaves 1.2 W (1.5 W − 0.3 W) for the drivers.
From Figures 7 and 9, VOL [1.75 V, and VOH [3.85 V.
The power dissipated in each driver is:
{(5.0 − 3.85) • 0.055} + (1.75 • 0.055) = 160 mW.
Since each driver dissipates 160 mW, the four drivers per
package could be used in this application.
Example 2: TA = 85°C, IOL = 27.8 mA, IOH = 20 mA for
each driver, VCC = 5.0 V, SOIC package. How many drivers
per package can be used?
Maximum allowable power dissipation is:
System Example
An example of a typical EIA−485 system is shown in
Figure 18. In this example, it is assumed each receiver’s
input characteristics correspond to 1.0 U.L. as defined in
Figure 17. Each “off” driver, with a maximum leakage of
±50 mA over the common mode range, presents a load of
[0.06 U.L. The total load for the active driver is therefore
8.3 unit loads, plus the parallel combination of the two
terminating resistors (60W). It is up to the system software
to control the driver Enable pins to ensure that only one
driver is active at any time.
PDmax + 130°C * 85°C + 0.53 W
85°CńW
Since the power supply current of 60 mA dissipates
300 mW, that leaves 230 mW (530 mW − 300 mW) for the
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9
MC75172B, MC75174B
Termination Resistors
Leaving off the terminations will generally result in
reflections which can have amplitudes of several volts
above VCC or below ground. These overshoots and
undershoots can disrupt the driver and/or receiver
operation, create false data, and in some cases damage
components on the bus.
Transmission line theory states that, in order to preserve
the shape and integrity of a waveform traveling along a
cable, the cable must be terminated in an impedance equal
to its characteristic impedance. In a system such as that
depicted in Figure 18, in which data can travel in both
directions, both physical ends of the cable must be
terminated. Stubs, leading to each receiver and driver,
should be as short as possible.
En
R
R
TTL
#1
TTL
TTL
D
#2
#3
En
TTL
D
RT
#1
5 “off” drivers (@ 0.06 U.L. each),
+8 receivers (@ 1.0 U.L. each) = 8.3 Unit Loads
RT = 120 W at each end of the cable.
120 W
Twisted
Pair
En
TTL
D
R
TTL
#2
#3
En
D
TTL
#4
R
TTL
#4
TTL
R
#6
En
TTL
D
RT
#6
En
R
TTL
#8
NOTES:
R
R
TTL
#7
TTL
#5
TTL
D
#5
1.Terminating resistors RT must be located at the physical ends of the cable.
2.Stubs should be as short as possible.
3.Circuit ground of all drivers and receivers must be connected via a dedicated wire within the cable.
Do not rely on chassis ground or power line ground.
Figure 18. Typical EIA−485 System
http://onsemi.com
10
MC75172B, MC75174B
COMPARING SYSTEM REQUIREMENTS
Characteristic
Symbol
EIA−485
EIA−422−A
V.11 and X.27
Zout
Not Specified
t 100 W
50 10 100 W
Open Circuit Voltage
Differential
Single−Ended
VOCD
VOCS
1.5 to 6.0 V
t 6.0 V
p 6.0 V
p 6.0 V
p 6.0 V, w/3.9 kW, Load
p 6.0 V, w/3.9 kW, Load
Loaded Differential Voltage
VOD
1.5 to 5.0 V, w/54 W load
q 2.0 V or q 0.5 VOCD,
w/100 W load
q 2.0 V or q 0.5 VOCD,
w/100 W load
Differential Voltage Balance
DVOD
t 200 mV
p 400 mV
t 400 mV
Output Common Mode Range
VCM
−7.0 to +12 V
Not Specified
Not Specified
Offset Voltage
VOS
−1.0 t VOS t 3.0 V
p 3.0 V
p 3.0 V
DVOS
t 200 mV
p 400 mV
t 400 mV
Short Circuit Current
IOS
p 250 mA for −7.0 to 12 V
p 150 mA to ground
p 150 mA to ground
Leakage Current (VCC = 0)
IOLK
Not Specified
p 100 mA to −0.25 V thru
6.0 V
p 100 mA to ± 0.25 V
Output Rise/Fall Time (Note 2)
tr, tf
p 0.3 TB, w/54 W/1150 pF
load
p 0.1 TB or p 20 ns, w/100
W load
p 0.1 TB or p 20 ns, w/100
W load
GENERATOR (Driver)
Output Impedance (Note 1)
Offset Voltage Balance
RECEIVER
Vth
± 200 mV
± 200 mV
± 300 mV
Input Bias Voltage
Vbias
p 3.0 V
p 3.0 V
p 3.0 V
Input Common Mode Range
Vcm
−7.0 to 12 V
−7.0 to 7.0 V
−7.0 to 7.0 V
Dynamic Input Impedance
Rin
Spec number of U.L.
q 4 kW
q 4 kW
Input Sensitivity
NOTES: 1. Compliance with V.11 and X.27 (Blue book) output impedance requires external resistors in series with the outputs of the
MC75172B and MC75174B.
2. TB = Bit time.
Additional Information
Copies of the EIA Recommendations (EIA−485 and EIA−422−A) can be obtained from the Electronics Industries
Association, Washington, D.C. (202−457−4966). Copies of the CCITT Recommendations (V.11 and X.27) can be obtained
from the United States Department of Commerce, Springfield, VA (703−487−4600).
ORDERING INFORMATION
Device
Operating Temperature Range
Package
MC75172BDW
SOIC−20WB
MC75172BDWG
SOIC−20WB
(Pb−Free)
MC75172BDWR2
SOIC−20WB
MC75172BDWR2G
SOIC−20WB
(Pb−Free)
MC75174BDW
MC75174BDWG
Shipping†
38 Units / Rail
1000 / Tape & Reel
SOIC−20WB
TA = − 40° to +85°C
SOIC−20WB
(Pb−Free)
MC75174BDWR2
SOIC−20WB
MC75174BDWR2G
SOIC−20WB
(Pb−Free)
MC75174BP
PDIP−16
MC75174BPG
PDIP−16
(Pb−Free)
38 Units / Rail
1000 / Tape & Reel
25 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE V
16
1
SCALE 1:1
D
A
16
9
E
H
E1
1
NOTE 8
b2
8
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
A1
C
D1
e
SEATING
PLANE
M
eB
END VIEW
16X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
GENERIC
MARKING DIAGRAM*
16
STYLE 1:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
STYLE 2:
PIN 1. COMMON DRAIN
2. COMMON DRAIN
3. COMMON DRAIN
4. COMMON DRAIN
5. COMMON DRAIN
6. COMMON DRAIN
7. COMMON DRAIN
8. COMMON DRAIN
9. GATE
10. SOURCE
11. GATE
12. SOURCE
13. GATE
14. SOURCE
15. GATE
16. SOURCE
98ASB42431B
PDIP−16
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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