MCR12DSMT4

MCR12DSM, MCR12DSN Sensitive Gate Silicon Controlled Rectifiers Reverse Blocking Thyristors Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control; CDI (Capacitive Discharge Ignition); and small engines. http://onsemi.com SCRs 12 AMPERES RMS 600 − 800 VOLTS Features • • • • • • Small Size Passivated Die for Reliability and Uniformity Low Level Triggering and Holding Characteristics Epoxy Meets UL 94 V−0 @ 0.125 in ESD Ratings: Human Body Model, 3B u 8000 V Machine Model, C u 400 V These are Pb−Free Devices G A MARKING DIAGRAMS MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol K 4 Value Unit YWW R1 2DSxG Peak Repetitive Off−State Voltage (Note 1) (TJ = −40 to 110°C, Sine Wave, 50 Hz to 60 Hz) MCR12DSM MCR12DSN VDRM, VRRM On−State RMS Current (180° Conduction Angles; TC = 75°C) IT(RMS) 12 A Average On−State Current (180° Conduction Angles; TC = 75°C) IT(AV) 7.6 A Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 110°C) ITSM 100 A Circuit Fusing Consideration (t = 8.3 msec) I2t 41 A2sec PGM 5.0 W PG(AV) 0.5 W Forward Peak Gate Current (Pulse Width ≤ 10 sec, TC = 75°C) IGM 2.0 A Operating Junction Temperature Range TJ −40 to 110 °C 1 Cathode °C 2 Anode Forward Peak Gate Power (Pulse Width ≤ 10 sec, TC = 75°C) Forward Average Gate Power (t = 8.3 msec, TC = 75°C) Storage Temperature Range V DPAK CASE 369C STYLE 4 June, 2013 − Rev. 7 4 1 Tstg 3 600 800 −40 to 150 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded. © Semiconductor Components Industries, LLC, 2013 1 2 1 IPAK CASE 369D STYLE 4 2 YWW R1 2DSxG 3 Y WW R12DSx G = Year = Work Week = Device Code x= M or N = Pb−Free Package PIN ASSIGNMENT 3 Gate 4 Anode ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: MCR12DSM/D MCR12DSM, MCR12DSN THERMAL CHARACTERISTICS Characteristic Thermal Resistance,− Junction−to−Case Thermal Resistance − Junction−to−Ambient Thermal Resistance − Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes (Note 3) Symbol Max Unit RJC RJA RJA 2.2 88 80 °C/W TL 260 °C ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristics Min Typ Max Unit − − − − 10 500 12.5 18 V OFF CHARACTERISTICS Peak Repetitive Forward or Reverse Blocking Current (Note 4) TJ = 25°C (VAK = Rated VDRM or VRRM; RGK = 1.0 K) TJ = 110°C IDRM, IRRM A ON CHARACTERISTICS Peak Reverse Gate Blocking Voltage, (IGR = 10 A) VGRM 10 Peak Reverse Gate Blocking Current, (VGR = 10 V) IGRM − − 1.2 A Peak Forward On−State Voltage (Note 5), (ITM = 20 A) VTM − 1.3 1.9 V 5.0 − 12 − 200 300 0.45 − 0.2 0.65 − − 1.0 1.5 − 0.5 − 1.0 − 6.0 10 0.5 − 1.0 − 6.0 10 − 2.0 5.0 2.0 10 − − 50 100 Gate Trigger Current (Continuous dc) (Note 6) (VD = 12 V, RL = 100 ) Gate Trigger Voltage (Continuous dc) (Note 6) (VD = 12 V, RL = 100 ) Holding Current (VD = 12 V, Initiating Current = 200 mA, RGK = 1 k) Latching Current (VD = 12 V, IG = 2.0 mA, RGK = 1 k) TJ = 25°C TJ = −40°C TJ = 25°C TJ = −40°C TJ = 110°C TJ = 25°C TJ = −40°C TJ = 25°C TJ = −40°C Turn−On Time (Source Voltage = 12 V, RS = 6.0 K, IT = 16 A(pk), RGK = 1.0 K) (VD = Rated VDRM, Rise Time = 20 ns, Pulse Width = 10 s) IGT VGT IH IL A V mA mA tgt s DYNAMIC CHARACTERISTICS Critical Rate of Rise of Off−State Voltage (VD = 0.67 x Rated VDRM, Exponential Waveform, RGK = 1.0 K, TJ = 110°C) dv/dt Critical Rate of Rise of On−State Current (IPK = 50 A, PW = 40 sec, diG/dt = 1 A/sec, IGT = 10 mA) di/dt V/s A/s 2. These ratings are applicable when surface mounted on the minimum pad sizes recommended. 3. 1/8″ from case for 10 seconds. 4. Ratings apply for negative gate voltage or RGK = 1.0 k. Devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage. 5. Pulse Test: Pulse Width ≤ 2.0 msec, Duty Cycle ≤ 2%. 6. RGK current not included in measurement. http://onsemi.com 2 MCR12DSM, MCR12DSN Voltage Current Characteristic of SCR + Current Symbol Parameter VDRM Peak Repetitive Off State Forward Voltage IDRM Peak Forward Blocking Current VRRM Peak Repetitive Off State Reverse Voltage IRRM Peak Reverse Blocking Current VTM Peak On State Voltage IH Holding Current Anode + VTM on state IH IRRM at VRRM Reverse Blocking Region (off state) Reverse Avalanche Region + Voltage IDRM at VDRM Forward Blocking Region (off state) 110 P(AV) , AVERAGE POWER DISSIPATION (WATTS) TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C) Anode − 105 100 95 90 dc 85  80 180°  = Conduction Angle 75 70 0 1.0 2.0  = 30° 3.0 4.0 60° 5.0 90° 120° 6.0 7.0 8.0 16 180° 120° 14 90°  12 60° dc  = Conduction Angle 10 8.0  = 30° 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 IT(AV), AVERAGE ON-STATE CURRENT (AMPS) IT(AV), AVERAGE ON-STATE CURRENT (AMPS) Figure 1. Average Current Derating Figure 2. On−State Power Dissipation http://onsemi.com 3 8.0 100 1.0 TYPICAL @ TJ = 25°C r(t) , TRANSIENT THERMAL RESISTANCE (NORMALIZED) I T, INSTANTANEOUS ON-STATE CURRENT (AMPS) MCR12DSM, MCR12DSN MAXIMUM @ TJ = 110°C 10 MAXIMUM @ TJ = 25°C 1.0 0.1 ZJC(t) = RJC(t)Sr(t) 0.01 0 2.0 1.0 3.0 5.0 4.0 0.1 10 1.0 100 10 K t, TIME (ms) Figure 3. On−State Characteristics Figure 4. Transient Thermal Response 1.0 VGT, GATE TRIGGER VOLTAGE (VOLTS) RGK = 1.0 K 100 GATE OPEN 10 1.0 -40 -25 0.1 -10 5.0 20 35 50 65 80 95 -40 -25 110 -10 5.0 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Typical Gate Trigger Current versus Junction Temperature Figure 6. Typical Gate Trigger Voltage versus Junction Temperature 10 110 10 RGK = 1.0 K RGK = 1.0 K IL, LATCHING CURRENT (mA) IH , HOLDING CURRENT (mA) 1000 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) 1000 I GT, GATE TRIGGER CURRENT ( A) 0.1 1.0 0.1 -40 -25 -10 5.0 20 35 50 65 80 95 1.0 0.1 -40 -25 110 -10 5.0 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. Typical Holding Current versus Junction Temperature Figure 8. Typical Latching Current versus Junction Temperature http://onsemi.com 4 110 MCR12DSM, MCR12DSN 10 1000 8.0 STATIC dv/dt (V/ s) IH, HOLDING CURRENT (mA) TJ = 25°C 6.0 IGT = 25 A 4.0 70°C 100 90°C TJ = 110°C 10 IGT = 10 A 2.0 0 1.0 100 1000 10 K 100 1000 RGK, GATE-CATHODE RESISTANCE (OHMS) RGK, GATE-CATHODE RESISTANCE (OHMS) Figure 9. Holding Current versus Gate−Cathode Resistance Figure 10. Exponential Static dv/dt versus Gate−Cathode Resistance and Junction Temperature 1000 1000 TJ = 110°C VD = 800 V TJ = 110°C 100 STATIC dv/dt (V/ s) STATIC dv/dt (V/ s) 400 V 600 V VPK = 800 V 10 1.0 100 IGT = 25 A IGT = 10 A 10 1.0 100 1000 1000 100 RGK, GATE-CATHODE RESISTANCE (OHMS) RGK, GATE-CATHODE RESISTANCE (OHMS) Figure 11. Exponential Static dv/dt versus Gate−Cathode Resistance and Peak Voltage Figure 12. Exponential Static dv/dt versus Gate−Cathode Resistance and Gate Trigger Current Sensitivity ORDERING INFORMATION Package Type Package Shipping† MCR12DSMT4G DPAK (Pb−Free) 369C 2500 / Tape & Reel MCR12DSN−1G IPAK (Pb−Free) 369D 75 Units / Rail MCR12DSNT4G DPAK (Pb−Free) 369C 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MCR12DSM, MCR12DSN PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE D A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 3.00 0.118 1.60 0.063 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− MCR12DSM, MCR12DSN PACKAGE DIMENSIONS IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MCR12DSM/D