MJE13003
SWITCHMODEt Series NPN
Silicon Power Transistor
These devices are designed for high−voltage, high−speed power
switching inductive circuits where fall time is critical. They are
particularly suited for 115 and 220 V SWITCHMODE applications
such as Switching Regulators, Inverters, Motor Controls,
Solenoid/Relay drivers and Deflection circuits.
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1.5 AMPERES
NPN SILICON POWER
TRANSISTORS
300 AND 400 VOLTS
40 WATTS
Features
• Reverse Biased SOA with Inductive Loads @ TC = 100_C
• Inductive Switching Matrix 0.5 to 1.5 A, 25 and 100_C
tc @ 1 A, 100_C is 290 ns (Typ)
• 700 V Blocking Capability
• SOA and Switching Applications Information
• Pb−Free Package is Available*
MAXIMUM RATINGS
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Symbol
Value
Unit
Collector−Emitter Voltage
Rating
VCEO(sus)
400
Vdc
Collector−Emitter Voltage
VCEV
700
Vdc
Emitter Base Voltage
VEBO
9
Vdc
IC
Adc
Collector Current
− Continuous
− Peak (Note 1)
ICM
1.5
3
Base Current
− Continuous
− Peak (Note 1)
IB
IBM
0.75
1.5
Adc
Emitter Current
− Continuous
− Peak (Note 1)
IE
IEM
2.25
4.5
Adc
Total Power Dissipation @ TA = 25_C
Derate above 25_C
PD
1.4
11.2
W
mW/_C
Total Power Dissipation @ TC = 25_C
Derate above 25_C
PD
40
320
W
mW/_C
TJ, Tstg
–65 to
+150
_C
Symbol
Max
Unit
Thermal Resistance, Junction−to−Case
RqJC
3.12
_C/W
Thermal Resistance, Junction−to−Ambient
RqJA
89
_C/W
Maximum Load Temperature for Soldering
Purposes: 1/8″ from Case for 5 Seconds
TL
275
_C
Operating and Storage Junction
Temperature Range
TO−225
CASE 77
STYLE 3
3
2 1
MARKING DIAGRAM
1 BASE
YWW
JE
13003G
2 COLLECTOR
3 EMITTER
THERMAL CHARACTERISTICS
Characteristic
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Pulse Test: Pulse Width = 5 ms, Duty Cycle ≤ 10%.
Y
WW
JE13003
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
MJE13003
TO−225
500 Units/Box
TO−225
(Pb−Free)
500 Units/Box
MJE13003G
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 2
1
Publication Order Number:
MJE13003/D
MJE13003
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ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Collector−Emitter Sustaining Voltage (IC = 10 mA, IB = 0)
VCEO(sus)
400
−
−
Vdc
Collector Cutoff Current
(VCEV = Rated Value, VBE(off) = 1.5 Vdc)
(VCEV = Rated Value, VBE(off) = 1.5 Vdc, TC = 100_C)
ICEV
−
−
−
−
1
5
Emitter Cutoff Current (VEB = 9 Vdc, IC = 0)
IEBO
−
−
1
OFF CHARACTERISTICS (Note 2)
mAdc
mAdc
SECOND BREAKDOWN
Second Breakdown Collector Current with bass forward biased
Clamped Inductive SOA with base reverse biased
IS/b
See Figure 11
−
RBSOA
See Figure 12
−
ON CHARACTERISTICS (Note 2)
DC Current Gain
(IC = 0.5 Adc, VCE = 2 Vdc)
(IC = 1 Adc, VCE = 2 Vdc)
hFE
Collector−Emitter Saturation Voltage
(IC = 0.5 Adc, IB = 0.1 Adc)
(IC = 1 Adc, IB = 0.25 Adc)
(IC = 1.5 Adc, IB = 0.5 Adc)
(IC = 1 Adc, IB = 0.25 Adc, TC = 100_C)
VCE(sat)
Base−Emitter Saturation Voltage
(IC = 0.5 Adc, IB = 0.1 Adc)
(IC = 1 Adc, IB = 0.25 Adc)
(IC = 1 Adc, IB = 0.25 Adc, TC = 100_C)
VBE(sat)
−
8
5
−
−
40
25
−
−
−
−
−
−
−
−
0.5
1
3
1
−
−
−
−
−
−
1
1.2
1.1
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Current−Gain − Bandwidth Product (IC = 100 mAdc, VCE = 10 Vdc, f = 1 MHz)
Output Capacitance (VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
fT
4
10
−
MHz
Cob
−
21
−
pF
td
−
0.05
0.1
ms
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time
Rise Time
Storage Time
(VCC = 125 Vdc, IC = 1 A,
IB1 = IB2 = 0.2 A, tp = 25 ms,
Duty Cycle v 1%)
Fall Time
tr
−
0.5
1
ms
ts
−
2
4
ms
tf
−
0.4
0.7
ms
tsv
−
1.7
4
ms
tc
−
0.29
0.75
ms
tfi
−
0.15
−
ms
Inductive Load, Clamped (Table 1, Figure 13)
Storage Time
Crossover Time
(IC = 1 A, Vclamp = 300 Vdc,
IB1 = 0.2 A, VBE(off) = 5 Vdc, TC = 100_C)
Fall Time
2. Pulse Test: PW = 300 ms, Duty Cycle v 2%.
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2
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
MJE13003
80
hFE , DC CURRENT GAIN
60
TJ = 150°C
40
30
25°C
20
−55 °C
10
8
VCE = 2 V
VCE = 5 V
6
4
0.02 0.03
0.05 0.07 0.1
0.2 0.3
0.5 0.7
IC, COLLECTOR CURRENT (AMP)
1
2
2
TJ = 25°C
1.6
1.2
IC = 0.1 A
1.5 A
0.4
0
0.002 0.005 0.01
0.02
0.05 0.1 0.2
IB, BASE CURRENT (AMP)
1
2
0.35
VBE(sat) @ IC/IB = 3
VBE(on) @ VCE = 2 V
1
0.3
V, VOLTAGE (VOLTS)
1.2
TJ = −55°C
25°C
0.8
25°C
0.6
0.05 0.07 0.1
0.2 0.3
0.25
IC/IB = 3
0.2
TJ = −55°C
0.15
25°C
0.1
150°C
150°C
0.4
0.02 0.03
0.05
0.5 0.7
1
0
0.02 0.03
2
0.05 0.07 0.1
0.2
0.3
0.5 0.7
1
IC, COLLECTOR CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
Figure 3. Base−Emitter Voltage
Figure 4. Collector−Emitter Saturation Region
104
2
500
VCE = 250 V
300
Cib
200
C, CAPACITANCE (pF)
103
TJ = 150°C
102
125°C
100°C
101
75°C
50°C
30
20
10
7
5
0.1 0.2
25°C
REVERSE
FORWARD
−0.2
0
+0.2
+0.4
VBE, BASE−EMITTER VOLTAGE (VOLTS)
+0.6
Figure 5. Collector Cutoff Region
Cob
0.5
1
2 5 10 20 50 100 200 500 1000
VR, REVERSE VOLTAGE (VOLTS)
Figure 6. Capacitance
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3
TJ = 25°C
100
70
50
100
10−1
−0.4
0.5
Figure 2. Collector Saturation Region
1.4
V, VOLTAGE (VOLTS)
1A
0.8
Figure 1. DC Current Gain
IC, COLLECTOR CURRENT (A)
μ
0.3 A 0.5 A
MJE13003
Table 1. Test Conditions for Dynamic Performance
RESISTIVE
SWITCHING
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
+5 V
TEST CIRCUITS
0.001 mF
DUTY CYCLE ≤ 10%
tr, tf ≤ 10 ns
2N222
2
1k
68
L
IB
1
k 2N2905
270
IC
RB
1
+5 Vk
1N4933
0.02 mF
NOTE
PW and VCC Adjusted for Desired IC
RB Adjusted for Desired IB1
CIRCUIT
VALUES
+125 V
MJE210
MR826*
47
100
1/2 W
Coil Data:
Ferroxcube Core #6656
Full Bobbin (~200 Turns) #20
T.U.T.
Vclamp
*SELECTED FOR ≥ 1 kV
5.1 k
VCE
51
TEST WAVEFORMS
TUT
SCOPE
RB
D1
−4.0
V
MJE200
− VBE(off)
GAP for 30 mH/2 A
Lcoil = 50 mH
VCC = 20 V
Vclamp = 300 Vdc
OUTPUT WAVEFORMS
IC
RC
33 1N4933
5V
PW
VCC
33
1N4933
VCC = 125 V
RC = 125 W
D1 = 1N5820 or Equiv.
RB = 47 W
+10.3 V
25 ms
tf CLAMPED
t1 Adjusted to
Obtain IC
IC(pk)
t
t1
VCE
tf
t1 ≈
VCEor
Vclamp
TIME
t2
t
t2 ≈
Lcoil (IC
pk)
VCC
Lcoil (IC
pk)
Vclamp
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4
Test Equipment
Scope−Tektronics
475 or Equivalent
0
− 8.5 V
tr, tf < 10 ns
Duty Cycle = 1.0%
RB and RC adjusted
for desired IB and IC
MJE13003
Vclamp
90% Vclamp
IC
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Table 2. Typical Inductive Switching Performance
ICPK
tsv
90% IC
trv
tfi
tti
tc
VCE
IB
10% Vclamp
90% IB1
10%
ICPK
2% IC
IC
AMP
TC
_C
tsv
ms
trv
ms
tfi
ms
tti
ms
tc
ms
0.5
25
100
1.3
1.6
0.23
0.26
0.30
0.30
0.35
0.40
0.30
0.36
1
25
100
1.5
1.7
0.10
0.13
0.14
0.26
0.05
0.06
0.16
0.29
1.5
25
100
1.8
3
0.07
0.08
0.10
0.22
0.05
0.08
0.16
0.28
TIME
Figure 7. Inductive Switching Measurements
NOTE: All Data Recorded in the Inductive Switching Circuit in Table 1
SWITCHING TIMES NOTE
In resistive switching circuits, rise, fall, and storage times
have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage
waveforms are not in phase. Therefore, separate
measurements must be made on each waveform to
determine the total switching time. For this reason, the
following new terms have been defined.
tsv = Voltage Storage Time, 90% IB1 to 10% Vclamp
trv = Voltage Rise Time, 10−90% Vclamp
tfi = Current Fall Time, 90−10% IC
tti = Current Tail, 10−2% IC
tc = Crossover Time, 10% Vclamp to 10% IC
An enlarged portion of the inductive switching
waveforms is shown in Figure 7 to aid in the visual identity
of these terms.
For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained
using the standard equation from AN−222:
PSWT = 1/2 VCCIC(tc)f
In general, t rv + t fi ] t c. However, at lower test currents
this relationship may not be valid.
As is common with most switching transistors, resistive
switching is specified at 25_C and has become a benchmark
for designers. However, for designers of high frequency
converter circuits, the user oriented specifications which
make this a “SWITCHMODE” transistor are the inductive
switching speeds (tc and tsv) which are guaranteed at 100_C.
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5
MJE13003
RESISTIVE SWITCHING PERFORMANCE
2
VCC = 125 V
IC/IB = 5
TJ = 25°C
1
tr
0.3
0.2
td @ VBE(off) = 5 V
0.1
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
2
1
0.7
0.5
0.07
0.05
tf
0.3
0.2
0.03
0.02
0.02 0.03
1
0.7
0.5
0.05 0.07 0.1
0.5 0.7 10
0.1
0.02 0.03
20
0.05 0.07 0.1
0.2
0.3
0.5 0.7
IC, COLLECTOR CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
Figure 8. Turn−On Time
Figure 9. Turn−Off Time
0.1
ZqJC(t) = r(t) RqJC
RqJC = 3.12°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
0.05
0.02
0.03
0.01
0.01
0.3
1
2
0.2
0.2
0.02
0.2
D = 0.5
0.3
0.1
0.07
0.05
VCC = 125 V
IC/IB = 5
TJ = 25°C
ts
3
t, TIME (s)
μ
t, TIME (s)
μ
0.7
0.5
10
7
5
0.01
SINGLE PULSE
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2 3
5
10 20
t, TIME OR PULSE WIDTH (ms)
Figure 10. Thermal Response
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6
50
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
100
200
500
1000
MJE13003
The Safe Operating Area figures shown in Figures 11 and 12 are
specified ratings for these devices under the test conditions
shown.
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 11 is based on TC = 25_C; T J(pk) is
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when TC ≥ 25_C. Second breakdown limitations do
not derate the same as thermal limitations. Allowable
current at the voltages shown on Figure 11 may be found at
any case temperature by using the appropriate curve on
Figure 13.
T J(pk) may be calculated from the data in Figure 10. At
high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations
imposed by second breakdown.
IC, COLLECTOR CURRENT (AMP)
10
5
2
100 ms
1
10 ms
5.0ms
dc
0.5
1.0 ms
TC = 25°C
0.2
THERMAL LIMIT (SINGLE PULSE)
BONDING WIRE LIMIT
SECOND BREAKDOWN LIMIT
CURVES APPLY BELOW RATED VCEO
0.1
0.0
5
0.02
0.01
5
MJE13003
10
20
50
100
200 300
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
500
Figure 11. Active Region Safe Operating
Area
REVERSE BIAS
IC, COLLECTOR CURRENT (AMP)
1.6
For inductive loads, high voltage and high current must be
sustained simultaneously during turn−off, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage−current conditions during
reverse biased turn−off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 12 gives RBSOA characteristics.
1.2
VBE(off) = 9 V
TJ ≤ 100°C
IB1 = 1 A
0.8
MJE13003
0.4
5V
3V
0
0
100
200 300
1.5 V
400
500
600
700
800
VCEV, COLLECTOR−EMITTER CLAMP VOLTAGE (VOLTS)
Figure 12. Reverse Bias Safe Operating Area
POWER DERATING FACTOR
1
SECOND BREAKDOWN
DERATING
0.8
0.6
THERMAL
DERATING
0.4
0.2
0
20
40
60
80
100
120
140
TC, CASE TEMPERATURE (°C)
Figure 13. Forward Bias Power Derating
SWITCHMODE is a trademark of Semiconductor Components Industries, LLC.
http://onsemi.com
7
160
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−225
CASE 77−09
ISSUE AD
4
DATE 25 MAR 2015
3 2
1
1 2
3
FRONT VIEW
BACK VIEW
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. NUMBER AND SHAPE OF LUGS OPTIONAL.
E
A1
Q
A
PIN 4
BACKSIDE TAB
DIM
A
A1
b
b2
c
D
E
e
L
L1
P
Q
D
P
1
2
3
L1
MILLIMETERS
MIN
MAX
2.40
3.00
1.00
1.50
0.60
0.90
0.51
0.88
0.39
0.63
10.60
11.10
7.40
7.80
2.04
2.54
14.50
16.63
1.27
2.54
2.90
3.30
3.80
4.20
GENERIC
MARKING DIAGRAM*
L
YWW
XX
XXXXXG
2X
b2
2X
e
b
FRONT VIEW
Y
= Year
WW
= Work Week
XXXXX = Device Code
G
= Pb−Free Package
c
SIDE VIEW
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLE 1:
PIN 1. EMITTER
2., 4. COLLECTOR
3. BASE
STYLE 2:
PIN 1. CATHODE
2., 4. ANODE
3. GATE
STYLE 3:
PIN 1. BASE
2., 4. COLLECTOR
3. EMITTER
STYLE 4:
PIN 1. ANODE 1
2., 4. ANODE 2
3. GATE
STYLE 5:
PIN 1. MT 1
2., 4. MT 2
3. GATE
STYLE 6:
PIN 1. CATHODE
2., 4. GATE
3. ANODE
STYLE 7:
PIN 1. MT 1
2., 4. GATE
3. MT 2
STYLE 8:
PIN 1. SOURCE
2., 4. GATE
3. DRAIN
STYLE 9:
PIN 1. GATE
2., 4. DRAIN
3. SOURCE
STYLE 10:
PIN 1. SOURCE
2., 4. DRAIN
3. GATE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42049B
TO−225
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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