MJE13005G
SWITCHMODEt Series
NPN Silicon Power
Transistors
These devices are designed for high−voltage, high−speed power
switching inductive circuits where fall time is critical. They are
particularly suited for 115 and 220 V SWITCHMODE applications
such as Switching Regulator’s, Inverters, Motor Controls,
Solenoid/Relay drivers and Deflection circuits.
Features
• VCEO(sus) 400 V
• Reverse Bias SOA with Inductive Loads @ TC = 100_C
• Inductive Switching Matrix 2 to 4 A, 25 and 100_C tc @ 3A,
http://onsemi.com
4 AMPERE
NPN SILICON
POWER TRANSISTOR
400 VOLTS − 75 WATTS
100_C is 180 ns (Typ)
• 700 V Blocking Capability
• SOA and Switching Applications Information
• These Devices are Pb−Free and are RoHS Compliant*
TO−220AB
CASE 221A−09
STYLE 1
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector−Emitter Voltage
VCEO(sus)
400
Vdc
Collector−Emitter Voltage
VCEV
700
Vdc
Emitter−Base Voltage
VEBO
9
Vdc
Collector Current
− Continuous
− Peak (Note 1)
IC
ICM
4
8
Adc
Base Current
− Continuous
− Peak (Note 1)
IB
IBM
2
4
Adc
Emitter Current
− Continuous
− Peak (Note 1)
IE
IEM
6
12
Adc
Total Device Dissipation @ TA = 25_C
Derate above 25°C
PD
2
0.016
W
W/_C
Total Device Dissipation @ TC = 25_C
Derate above 25°C
PD
75
0.6
W
W/_C
TJ, Tstg
−65 to
+150
_C
Symbol
Max
Unit
Thermal Resistance, Junction−to−Ambient
RqJA
62.5
_C/W
Thermal Resistance, Junction−to−Case
RqJC
1.67
_C/W
TL
275
_C
Operating and Storage Junction
Temperature Range
1
Maximum Lead Temperature for Soldering
Purposes 1/8″ from Case for 5 Seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 5 ms, Duty Cycle ≤ 10%.
3
MARKING DIAGRAM
MJE13005G
AY WW
A
Y
WW
G
THERMAL CHARACTERISTICS
Characteristics
2
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
MJE13005G
Package
Shipping
TO−220
(Pb−Free)
50 Units / Rail
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2010
August, 2010 − Rev. 9
1
Publication Order Number:
MJE13005/D
MJE13005G
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ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
VCEO(sus)
400
−
−
Vdc
−
−
−
−
1
5
−
1
OFF CHARACTERISTICS (Note 2)
Collector−Emitter Sustaining Voltage
(IC = 10 mA, IB = 0)
Collector Cutoff Current
(VCEV = Rated Value, VBE(off) = 1.5 Vdc)
(VCEV = Rated Value, VBE(off) = 1.5 Vdc, TC = 100_C)
ICEV
mAdc
Emitter Cutoff Current
(VEB = 9 Vdc, IC = 0)
IEBO
−
IS/b
−
See Figure 11
RBSOA
−
See Figure 12
mAdc
SECOND BREAKDOWN
Second Breakdown Collector Current with base forward biased
Clamped Inductive SOA with Base Reverse Biased
ON CHARACTERISTICS (Note 2)
DC Current Gain
(IC = 1 Adc, VCE = 5 Vdc)
(IC = 2 Adc, VCE = 5 Vdc)
hFE
−
10
8
−
−
60
40
−
−
−
−
−
−
−
−
0.5
0.6
1
1
−
−
−
−
−
−
1.2
1.6
1.5
fT
4
−
−
MHz
Cob
−
65
−
pF
td
−
0.025
0.1
ms
tr
−
0.3
0.7
ms
ts
−
1.7
4
ms
tf
−
0.4
0.9
ms
tsv
−
0.9
4
ms
tc
−
0.32
0.9
ms
tfi
−
0.16
−
ms
Collector−Emitter Saturation Voltage
(IC = 1 Adc, IB = 0.2 Adc)
(IC = 2 Adc, IB = 0.5 Adc)
(IC = 4 Adc, IB = 1 Adc)
(IC = 2 Adc, IB = 0.5 Adc, TC = 100_C)
VCE(sat)
Base−Emitter Saturation Voltage
(IC = 1 Adc, IB = 0.2 Adc)
(IC = 2 Adc, IB = 0.5 Adc)
(IC = 2 Adc, IB = 0.5 Adc, TC = 100_C)
VBE(sat)
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Current−Gain − Bandwidth Product
(IC = 500 mAdc, VCE = 10 Vdc, f = 1 MHz)
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
SWITCHING CHARACTERISTICS
Resistive Load (Table 2)
Delay Time
Rise Time
Storage Time
(VCC = 125 Vdc, IC = 2 A,
IB1 = IB2 = 0.4 A, tp = 25 ms,
Duty Cycle v 1%)
Fall Time
Inductive Load, Clamped (Table 2, Figure 13)
Voltage Storage Time
Crossover Time
Fall Time
(IC = 2 A, Vclamp = 300 Vdc,
IB1 = 0.4 A, VBE(off) = 5 Vdc, TC = 100_C)
2. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
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2
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
MJE13005G
100
hFE, DC CURRENT GAIN
70
TJ = 150°C
50
25°C
30
20
-55°C
10
VCE = 2 V
VCE = 5 V
7
5
0.04 0.06
0.1
0.2
0.4 0.6
1
IC, COLLECTOR CURRENT (AMP)
2
4
2
TJ = 25°C
1.6
IC = 1 A
VCE(sat) , COLLECTOR-EMITTER SATURATION
VOLTAGE (VOLTS)
VBE, BASE-EMITTER VOLTAGE (VOLTS)
0.9
TJ = -55°C
25°C
0.7
25°C
0.5
150°C
0.3
0.04 0.06
0.1
0.2
0.4
0.6
1
2
4
0.4
0
0.03
0.05
0.1
IC/IB = 4
0.45
TJ = -55°C
0.35
25°C
0.25
0.15
150°C
0.05
0.04 0.06
0.1
0.2
0.4
0.6
1
2
4
Figure 4. Collector−Emitter Saturation Voltage
2k
C, CAPACITANCE (pF)
IC, COLLECTOR CURRENT (A)
μ
3
Figure 3. Base−Emitter Voltage
TJ = 150°C
125°C
100°C
75°C
50°C
25°C
0.1
-0.4
2
IC, COLLECTOR CURRENT (AMP)
1k
1
1
0.55
VCE = 250 V
10
0.2 0.3
0.5 0.7
IB, BASE CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
10 k
100
4A
Figure 2. Collector Saturation Region
1.3
VBE(sat) @ IC/IB = 4
VBE(on) @ VCE = 2 V
3A
0.8
Figure 1. DC Current Gain
1.1
2A
1.2
REVERSE
FORWARD
-0.2
0
+0.2
+0.4
VBE, BASE-EMITTER VOLTAGE (VOLTS)
Cib
1k
700
500
300
200
100
70
50
30
20
0.3
+0.6
Figure 5. Collector Cutoff Region
Cob
0.5
1 3 5
10
30
50
VR, REVERSE VOLTAGE (VOLTS)
Figure 6. Capacitance
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3
100
300
MJE13005G
ICPK
Vclamp
90% Vclamp
IC
tsv
90% IC
trv
tfi
tti
tc
VCE
10% Vclamp
IB
90% IB1
10%
ICPK
2% IC
TIME
Figure 7. Inductive Switching Measurements
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Table 1. Typical Inductive Switching Performance
IC
AMP
TC
_C
tsv
ns
trv
ns
tfi
ns
tti
ns
tc
ns
2
25
100
600
900
70
110
100
240
80
130
180
320
3
25
100
650
950
60
100
140
330
60
100
200
350
4
25
100
550
850
70
110
160
350
100
160
220
390
NOTE: All Data recorded in the inductive Switching Circuit In Table 2.
SWITCHING TIMES NOTE
In resistive switching circuits, rise, fall, and storage times
have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage
waveforms are not in phase. Therefore, separate
measurements must be made on each waveform to
determine the total switching time. For this reason, the
following new terms have been defined.
tsv = Voltage Storage Time, 90% IB1 to 10% Vclamp
trv = Voltage Rise Time, 10−90% Vclamp
tfi = Current Fall Time, 90−10% IC
tti = Current Tail, 10−2% IC
tc = Crossover Time, 10% Vclamp to 10% IC
An enlarged portion of the inductive switching
waveforms is shown in Figure 7 to aid in the visual identity
of these terms.
For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained
using the standard equation from AN−222:
PSWT = 1/2 VCCIC(tc)f
In general, t rv + t fi ] tc. However, at lower test currents
this relationship may not be valid.
As is common with most switching transistors, resistive
switching is specified at 25°C and has become a benchmark
for designers. However, for designers of high frequency
converter circuits, the user oriented specifications which
make this a “SWITCHMODE” transistor are the inductive
switching speeds (tc and tsv) which are guaranteed at 100_C.
RESISTIVE SWITCHING PERFORMANCE
10
1
VCC = 125 V
IC/IB = 5
TJ = 25°C
0.5
tr
t, TIME (s)
μ
t, TIME (s)
μ
0.2
0.1
0.05
2
1
0.5
td @ VBE(off) = 5 V
0.3
0.02
0.01
0.04
VCC = 125 V
IC/IB = 5
TJ = 25°C
ts
5
tf
0.2
0.1
0.2
0.4
1
2
0.1
0.04
4
0.1
0.2
0.5
1
IC, COLLECTOR CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
Figure 8. Turn−On Time
Figure 9. Turn−Off Time
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4
2
4
MJE13005G
Table 2. Test Conditions for Dynamic Performance
RESISTIVE
SWITCHING
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
+5 V
VCC
1N4933 33
+125 V
MJE210
TEST CIRCUITS
0.001 mF
L
RC
5V
PW
DUTY CYCLE ≤ 10%
tr, tf ≤ 10 ns
MR826*
33 1N4933
2N222
2
1k
68
1k
+5 V
Vclamp
IC
RB
5.1 k
IB
TUT
*SELECTED FOR ≥ 1 kV
D1
VCE
51
-4.0
V
2N2905
MJE200
47 100
1/2 W
NOTE
PW and VCC Adjusted for Desired IC
RB Adjusted for Desired IB1
CIRCUIT
VALUES
T.U.T.
1k
1N493
3
0.02 mF 270
Coil Data:
Ferroxcube Core #6656
Full Bobbin (~16 Turns) #16
- VBE(off)
GAP for 200 mH/20 A
Lcoil = 200 mH
VCC = 125 V
RC = 62 W
D1 = 1N5820 or Equiv.
RB = 22 W
VCC = 20 V
Vclamp = 300 Vdc
TEST WAVEFORMS
OUTPUT WAVEFORMS
tf CLAMPED
tf UNCLAMPED ≈ t2
IC
t
t1
VCE
1
0.7
0.5
t1 ≈
tf
VCE or
Vclamp
t2 ≈
Lcoil (IC )
pk
VCC
0
Test Equipment
Scope−Tektronics
475 or Equivalent
-8 V
tr, tf < 10 ns
Duty Cycle = 1.0%
RB and RC adjusted
for desired IB and IC
Lcoil (IC )
pk
Vclamp
t
25 ms
t2
D = 0.5
0.3
0.2
0.2
0.1
0.1
0.02
0.03
0.01
0.02
SINGLE PULSE
0.02
0.05
0.1
P(pk)
ZqJC(t) = r(t) RqJC
RqJC = 1.67°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) ZqJC(t)
0.05
0.07
0.05
0.01
0.01
+10 V
t1 ADJUSTED TO
OBTAIN IC
IC(pk)
TIME
r(t), TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
SCOPE
RB
0.2
0.5
1
2
5
t, TIME (ms)
10
20
Figure 10. Typical Thermal Response [ZqJC(t)]
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5
t1
t2
DUTY CYCLE, D = t1/t2
50
100
200
500
1k
MJE13005G
SAFE OPERATING AREA INFORMATION
The Safe Operating Area Figures 11 and 12 are specified ratings for these devices under the test conditions shown.
4
5
2
IC(pk) , COLLECTOR CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
10
500 ms
5 ms
dc
1
0.5
1 ms
0.2
0.1
0.05
0.02
MJE13005
0.01
5
7
10
20
30
50
70 100
200 300
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
TC ≤ 100°C
IB1 = 2.0 A
3
2
VBE(off) = 9 V
1
MJE13005
0
500
400
0
100
200
300
400
500
600
5V
3V
1.5 V
700
800
VCE, COLLECTOR-EMITTER CLAMP VOLTAGE (VOLTS)
Figure 11. Forward Bias Safe Operating Area
Figure 12. Reverse Bias Switching Safe Operating Area
FORWARD BIAS
REVERSE BIAS
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 11 is based on TC = 25_C; T J(pk) is
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when TC ≥ 25_C. Second breakdown limitations do
not derate the same as thermal limitations. Allowable
current at the voltages shown on Figure 11 may be found at
any case temperature by using the appropriate curve on
Figure 13.
T J(pk) may be calculated from the data in Figure 10. At
high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations
imposed by second breakdown.
For inductive loads, high voltage and high current must be
sustained simultaneously during turn−off, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage−current conditions during
reverse biased turn−off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 12 gives the complete RBSOA
characteristics.
POWER DERATING FACTOR
1
SECOND BREAKDOWN
DERATING
0.8
0.6
THERMAL
DERATING
0.4
0.2
0
20
40
60
80
100
120
140
TC, CASE TEMPERATURE (°C)
Figure 13. Forward Bias Power Derating
SWITCHMODE is a trademark of Semiconductor Components Industries, LLC.
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6
160
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220
CASE 221A
ISSUE AK
DATE 13 JAN 2022
SCALE 1:1
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
BASE
EMITTER
COLLECTOR
EMITTER
STYLE 3:
PIN 1.
2.
3.
4.
CATHODE
ANODE
GATE
ANODE
STYLE 4:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
STYLE 5:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 6:
PIN 1.
2.
3.
4.
ANODE
CATHODE
ANODE
CATHODE
STYLE 7:
PIN 1.
2.
3.
4.
CATHODE
ANODE
CATHODE
ANODE
STYLE 8:
PIN 1.
2.
3.
4.
CATHODE
ANODE
EXTERNAL TRIP/DELAY
ANODE
STYLE 9:
PIN 1.
2.
3.
4.
GATE
COLLECTOR
EMITTER
COLLECTOR
STYLE 10:
PIN 1.
2.
3.
4.
GATE
SOURCE
DRAIN
SOURCE
STYLE 11:
PIN 1.
2.
3.
4.
DRAIN
SOURCE
GATE
SOURCE
STYLE 12:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
NOT CONNECTED
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42148B
TO−220
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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