www.fairchildsemi.com
ML4800
Power Factor Correction and PWM Controller
Combo
Features
General Description
• Internally synchronized leading-edge PFC and trailingedge PWM in one IC
• TriFault Detect™ for UL1950 compliance and enhanced
safety
• Slew rate enhanced transconductance error amplifier for
ultra-fast PFC response
• Low power: 200µA startup current, 5.5mA operating
current
• Low total harmonic distortion, high PF
• Reduced ripple current in storage capacitor between PFC
and PWM sections
• Average current, continuous boost leading edge PFC
• PWM configurable for current-mode or voltage mode
operation
• Current fed gain modulator for improved noise immunity
• Overvoltage and brown-out protection, UVLO, and soft
start
The ML4800 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching FETs,
and results in a power supply that fully complies with
IEC1000-3-2 specification. Intended as a BiCMOS version
of the industry-standard ML4824, the ML4800 includes
circuits for the implementation of leading edge, average
current, “boost” type power factor correction and a trailing
edge, pulse width modulator (PWM). It also includes a
TriFault Detect™ function to help ensure that no unsafe
conditions will result from single component failure in the
PFC. Gate-drivers with 1A capabilities minimize the need
for external driver circuits. Low power requirements improve
efficiency and reduce component costs.
An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brownout
protection. The PWM section can be operated in current or
voltage mode, at up to 250kHz, and includes an accurate
50% duty cycle limit to prevent transformer saturation.
Block Diagram
16
VFB
VEA
-
15
2.5V
13
1
POWER FACTOR CORRECTOR
IEAO
VEAO
0.5V
1.6kΩ
+
IAC
IEA
+
VCC
+
-
2.75V
-
-1V
+
-
GAIN
MODULATOR
VRMS
-
7.5V
REFERENCE
S
Q
R
Q
S
Q
R
Q
S
Q
R
Q
VREF
14
PFC OUT
1.6kΩ
ISENSE
17V
+
-
2
4
VCC
OVP
+
TRI-FAULT
PFC ILIMIT
12
3
RAMP 1
OSCILLATOR
7
RAMP 2
DUTY CYCLE
LIMIT
8
VDC
6
1.25V
VCC
SS
PWM OUT
-
25µA
5
DC ILIMIT
9
+
+
VFB
-
2.45V
+
VIN OK
1.0V
+
11
DC ILIMIT
VREF
PULSE WIDTH MODULATOR
VCC
UVLO
REV. 1.0.5 9/25/01
ML4800
PRODUCT SPECIFICATION
Pin Configuration
ML4800
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N)
IEAO 1
IAC 2
ISENSE 3
VRMS 4
SS 5
VDC 6
16 VEAO
15 VFB
14 VREF
13 VCC
12 PFC OUT
11 PWM OUT
RAMP 1 7
10 GND
RAMP 2 8
9
DC ILIMIT
TOP VIEW
Pin Description
2
Pin
Name
Function
1
IEAO
2
IAC
PFC AC line reference input to Gain Modulator
3
ISENSE
Current sense input to the PFC Gain Modulator
4
VRMS
PFC Gain Modulator RMS line voltage compensation input
5
SS
Connection point for the PWM soft start capacitor
6
VDC
PWM voltage feedback input
7
RAMP 1
Oscillator timing node; timing set by RTCT
8
RAMP 2
When in current mode, this pin functions as the current sense input; when in voltage mode,
it is the PWM modulation ramp input.
PWM cycle-by-cycle current limit comparator input
Slew rate enhanced PFC transconductance error amplifier output
9
DC ILIMIT
10
GND
11
PWM OUT
PWM driver output
12
PFC OUT
PFC driver output
13
VCC
Positive supply
14
VREF
Buffered output for the internal 7.5V reference
15
VFB
PFC transconductance voltage error amplifier input
16
VEAO
Ground
PFC transconductance voltage error amplifier output
REV. 1.0.5 9/25/01
PRODUCT SPECIFICATION
ML4800
Abolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
Parameter
Min.
Max.
Units
18
V
VCC
ISENSE Voltage
-5
0.7
V
GND - 0.3
VCCZ + 0.3
V
IREF
10
mA
IAC Input Current
10
mA
Peak PFC OUT Current, Source or Sink
1
A
Voltage on Any Other Pin
Peak PWM OUT Current, Source or Sink
1
A
PFC OUT, PWM OUT Energy Per Cycle
1.5
µJ
Junction Temperature
150
°C
150
°C
Lead Temperature (Soldering, 10 sec)
260
°C
Thermal Resistance (θJA)
Plastic DIP
Plastic SOIC
80
105
°C/W
°C/W
Min
.Max.
Units
ML4800CX
0
70
°C
ML4800IX
-40
85
°C
Storage Temperature Range
-65
Operating Conditions
Temperature Range
Electrical Characteristics
Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
Voltage Error Amplifier
Transconductance
0
VNON INV = VINV, VEAO = 3.75V
Feedback Reference Voltage
Input Bias Current
30
2.43
Note 2
Output High Voltage
6.0
Output Low Voltage
5
V
65
90
µΩ
2.5
2.57
V
-0.5
-1.0
µA
6.7
0.1
Ω
Input Voltage Range
V
0.4
V
Source Current
VIN = ±0.5V, VOUT = 6V
-40
-140
µA
Sink Current
VIN = ±0.5V, VOUT = 1.5V
40
140
µA
50
60
dB
50
60
dB
Open Loop Gain
Power Supply Rejection Ratio
11V < VCC < 16.5V
Current Error Amplifier
Transconductance
Input Offset Voltage
REV. 1.0.5 9/25/01
-1.5
VNON INV = VINV, VEAO = 3.75V
2
V
50
100
150
µΩ
0
4
15
mV
Ω
Input Voltage Range
3
ML4800
PRODUCT SPECIFICATION
Electrical Characteristics (Continued)
Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
Min.
Input Bias Current
Output High Voltage
Typ.
Max. Units
-0.5
-1.0
6.0
6.7
Output Low Voltage
0.65
µA
V
1.0
V
Source Current
VIN = ±0.5V, VOUT = 6V
-40
-104
µA
Sink Current
VIN = ±0.5V, VOUT = 1.5V
40
160
µA
60
70
dB
60
75
dB
Threshold Voltage
2.65
2.75
2.85
V
Hysteresis
175
250
325
mV
2.65
2.75
2.85
V
2
4
ms
0.4
0.5
0.6
V
Threshold Voltage
-0.9
-1.0
-1.1
V
(PFC ILIMIT VTH - Gain
Modulator Output)
120
220
Open Loop Gain
Power Supply Rejection Ratio
11V < VCC < 16.5V
OVP Comparator
Tri-Fault Detect
Fault Detect HIGH
Time to Fault Detect HIGH
VFB = VFAULT DETECT LOW to
VFB = OPEN. 470pF from VFB to
GND
Fault Detect LOW
PFC ILIMIT Comparator
Delay to Output
mV
150
300
ns
1.0
1.05
V
Input Bias Current
±0.3
±1
µA
Delay to Output
150
300
ns
DC ILIMIT Comparator
Threshold Voltage
0.95
VIN OK Comparator
Threshold Voltage
2.35
2.45
2.55
V
Hysteresis
0.8
1.0
1.2
V
0.60
0.80
1.05
GAIN Modulator
Gain (Note 3)
IAC = 100µA, VRMS = VFB = 0V
IAC = 50µA, VRMS = 1.2V, VFB = 0V
1.8
2.0
2.40
IAC = 50µA, VRMS = 1.8V, VFB = 0V
0.85
1.0
1.25
IAC = 100µA, VRMS = 3.3V, VFB = 0V
0.20
0.30
0.40
Bandwidth
IAC = 100µA
Output Voltage
IAC = 350µA, VRMS = 1V, VFB = 0V
10
MHz
0.60
0.75
0.9
V
71
76
81
kHz
Oscillator
Initial Accuracy
TA = 25°C
Voltage Stability
11V < VCC < 16.5V
Temperature Stability
Total Variation
Ramp Valley to Peak Voltage
4
Line, Temp
1
%
2
%
68
84
2.5
kHz
V
REV. 1.0.5 9/25/01
PRODUCT SPECIFICATION
ML4800
Electrical Characteristics (Continued)
Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
PFC Dead Time
CT Discharge Current
Min.
Typ.
350
Max. Units
650
ns
VRAMP 2 = 0V, VRAMP 1 = 2.5V
3.5
5.5
7.5
mA
Output Voltage
TA = 25°C, I(VREF) = 1mA
7.4
7.5
7.6
V
Line Regulation
11V tDEADTIME) that the
operating frequency can typically be approximated by:
1
f OSC = ---------------t RAMP
(5)
EXAMPLE:
For the application circuit shown in the data sheet, with the
oscillator running at:
1
f OSC = 100kHz = ---------------t RAMP
The DC ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC
and inhibits the PWM if this voltage on VFB is less than its
nominal 2.45V. Once this voltage reaches 2.45V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start begins.
PWM Control (RAMP 2)
The dead time of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator dead time, the Maximum PWM Duty Cycle is
typically 45%. In many applications, care should be taken
that CT not be made so large as to extend the Maximum Duty
Cycle beyond 50%. This can be accomplished by using a
stable 390pF capacitor for CT.
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
current transformer. In voltage mode, it is the input for a
ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), that will have a minimum value of
zero volts and should have a peak value of approximately 5V.
In voltage mode operation, feedforward from the PFC output
buss is an excellent way to derive the timing ramp for the
PWM stage.
PWM SECTION
Soft Start
Solving for RT x CT yields 1.96 x 10-4. Selecting standard
components values, CT = 390pF, and RT = 51.1kΩ.
Pulse Width Modulator
The PWM section of the ML4800 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or voltage
mode operation. In current-mode applications, the PWM
ramp (RAMP 2) is usually derived directly from a current
sensing resistor or current transformer in the primary of the
10
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed by
the following equation:
25µA
C SS = t DELAY × --------------1.25V
(6)
REV. 1.0.5 9/25/01
PRODUCT SPECIFICATION
ML4800
function, it is important to limit the current through the
Zener to avoid overheating or destroying it. This can be
easily done with a single resistor in series with the Vcc pin,
returned to a bias supply of typically 18V to 20V. The
resistor’s value must be chosen to meet the operating current
requirement of the ML4800 itself (8.5mA, max.) plus the
current required by the two gate driver outputs.
where CSS is the required soft start capacitance, and tDELAY
is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at least
5ms.
Solving for the minimum value of CSS:
25µA
Css = 5ms × --------------- = 100nF
1.25V
EXAMPLE:
With a VBIAS of 20V, a VCC of 15V and the ML4800 driving
a total gate charge of 90nC at 100kHz (e.g., 1 IRF840
MOSFET and 2 IRF820 MOSFETs), the gate driver current
required is:
(6a)
Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the SS
capacitor and activation of the PWM section can result if
VFB is in the hysteresis band of the VIN OK comparator at
start-up. The magnitude of VFB at start-up is related both to
line voltage and nominal PFC output voltage. Typically, a
1.0µF soft start capacitor will allow time for V FB and PFC
out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and
265Vrms.
I2
I1
+
V BIAS – V CC
R BIAS = --------------------------------I CC + I G + I Z
(8)
Choose RBIAS = 240Ω.
The ML4800 should be locally bypassed with a 1.0µF
ceramic capacitor. In most applications, an electrolytic
capacitor of between 47µF and 220µF is also required across
the part, both for filtering and as part of the start-up bootstrap
circuitry.
The ML4800 is a voltage-fed part. It requires an external
15V, ±10% (or better) shunt voltage regulator, or some other
VCC regulator, to regulate the voltage supplied to the part at
15V nominal. This allows low power dissipation while at the
same time delivering 13V nominal gate drive at the PWM
OUT and PFC OUT outputs. If using a Zener diode for this
SW2
(7)
20V – 15V
R BIAS = -------------------------------------------------- = 250Ω
6mA + 9mA + 5mA
Generating VCC
L1
I GATEDRIVE = 100kHz × 90nC = 9mA
I3
I4
VIN
RL
SW1
DC
C1
RAMP
VEAO
REF
U3
+
–EA
TIME
DFF
RAMP
OSC
U4
CLK
+
–
U1
R
Q
D U2
Q
CLK
VSW1
TIME
Figure 4. Typical Trailing Edge Control Scheme
REV. 1.0.5 9/25/01
11
ML4800
PRODUCT SPECIFICATION
Leading/Trailing Modulation
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is
reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure
4 shows a typical trailing edge control scheme.
Typical Applications
Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application Note
33.
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 5 shows a leading
edge control scheme.
SW2
L1
I2
I1
+
I3
I4
VIN
RL
SW1
DC
C1
RAMP
VEAO
REF
U3
+
EA
–
RAMP
OSC
U4
CLK
VEAO
+
–
CMP
U1
TIME
DFF
R
Q
D U2
Q
CLK
VSW1
TIME
Figure 5. Typical Leading Edge Control Scheme
12
REV. 1.0.5 9/25/01
REV. 1.0.5 9/25/01
R39
33Ω
R7
1.2Ω
C1
0.47µF
D15
1N914
D13
1N914
D14
1N914
C19
1.0µF
R4
13.2kΩ
C3
R3
0.22µF 100kΩ
C2
0.47µF
R8
1.2Ω
R2
357kΩ
R1
357kΩ
BR1
4A, 600V
KBL06
R10
249kΩ
C26
47µF
R9
249kΩ
R27
82kΩ
C18
470pF
R20
22Ω
R38
42.2kΩ
8
7
6
5
4
3
2
1
RAMP 2
RAMP1
VDC
SS
VRMS
ISENSE
IAC
IEAO
VFB
VCC
VREF
DC ILMIT
GND
PWM OUT
PFC OUT
U1
VDC
C6 1.5nF
ML4800
R12 68.1k
C5
100µF
9
10
11
12
13
14
15
16
C28
220pF
C12
10µF
35V
C4
4.7nF
C7 150pF
R28
240Ω
IRF840A
Q1
IRF840A
D2
15V
1N4744A
R16 10kΩ
C11
220pF
Q1G
D1
8A
FES16JT
D7, D8, D10; 1N966B
D3, D5, D6, D12; UF4005
D4; 1N4733A
D2; 1N4744A
D11; MBR2545CT
L1; PREMIER MAGNETICS TSD-1047
L2; PREMIER MAGNETICS VTP-05007
L3; PREMIER MAGNETICS TSD-904
T1; PREMIER MAGNETICS PMGD-03
T2; PREMIER MAGNETICS TSD-735
UNUSED DESIGNATORS; C14, C16, C17, C27, C29, C33, D3, D9, R42, R43, R36, R35
RT/CT
R6
1.2Ω
NOTE:
R5
1.2Ω
ISENSE
AC INPUT
85 TO 260V
F1
3.15A
L1
D8
R14
383kΩ
R13
383kΩ
R17
3Ω
R15
4.99kΩ
C31
330pF
C13
0.22µF
REF
1N4733A
D4
5.1V
R22
2.2Ω
C8
150µF
R11
412kΩ
D11A
J8
PRI GND
C9
15nF
R26
10kΩ
R25
10kΩ
2N3904
Q4
D11B
L2
C10
10µF
R30
1.5kΩ
R29
1.2kΩ
C21
1500µF
U3
TL431A
VDC
R40
470Ω
U2
MOC8112
C24
0.47µF
VBUSS
MBR2545CT
T2C
D6
600V
D5
600V
PWM
ILIMIT
IRF820A
Q3
Q2
IRF820A
R37 1kΩ
C15
1.0µF
VCC
R23
220Ω
R21
2.2Ω
Q3G
D7
16V
R24
10kΩ
R19
33Ω
D10
C20
0.47µF
R18
33Ω
T1A
VFB
T1B
C25
0.1µF
Q2G
D12
R32
8.66kΩ
C30
1000µF
R33
2.26kΩ
C23
10nF
R31
10kΩ
R44
10kΩ
C22
10µF
C32
0.47µF
L3
12V
RETURN
12V RET
R34
240Ω
12V, 100W
12V
PRODUCT SPECIFICATION
ML4800
Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33
13
ML4800
PRODUCT SPECIFICATION
Ordering Information
Part Number
Temperature Range
Package
ML4800CP
0°C to 70°C
16-Pin PDIP (P16)
ML4800CS
0°C to 70°C
16-Pin Narrow SOIC (S16N)
ML4800IP
-40°C to 85°C
16-Pin PDIP (P16)
ML4800IS
-40°C to 85°C
16-Pin Narrow SOIC (S16N)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury of the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9/25/01 0.0m 001
Stock#DS30004800
2001 Fairchild Semiconductor Corporation
工商网监
湘ICP备2023018690号
