MLD1N06CLT4G

MLD1N06CL Power MOSFET 1 Amp, 62 Volts, Logic Level N−Channel DPAK The MLD1N06CL is designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontrol unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high in−rush current or a shorted load condition could occur. This Logic Level Power MOSFET features current limiting for short circuit protection, integrated Gate−Source clamping for ESD protection and integral Gate−Drain clamping for over−voltage protection and technology for low on−resistance. No additional gate series resistance is required when interfacing to the output of a MCU, but a 40 kW gate pulldown resistor is recommended to avoid a floating gate condition. The internal Gate−Source and Gate−Drain clamps allow the device to be applied without use of external transient suppression components. The Gate−Source clamp protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The Gate−Drain clamp protects the MOSFET drain from the avalanche stress that occurs with inductive loads. Their unique design provides voltage clamping that is essentially independent of operating temperature. www.onsemi.com V(BR)DSS RDS(on) TYP ID MAX 62 V (Clamped) 750 mW 1.0 A N−Channel R1 G R2 S Features MARKING DIAGRAM • Pb−Free Package is Available 4 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS Clamped Vdc Drain−to−Gate Voltage (RGS = 1.0 MW) VDGR Clamped Vdc VGS ±10 Vdc ID IDM Self−limited 1.8 Adc Apk PD 40 W TJ, Tstg −50 to 150 °C ESD 2.0 kV Rating Gate−to−Source Voltage − Continuous Drain Current − Continuous − Single Pulse Total Power Dissipation Operating and Storage Temperature Range Electrostatic Discharge Voltage (Human Model) THERMAL CHARACTERISTICS Thermal Resistance Junction−to−Case Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds RqJC RqJA RqJA 3.12 100 71.4 TL 260 °C/W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. When surface mounted to an FR−4 board using the minimum recommended pad size. 2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size. © Semiconductor Components Industries, LLC, 2008 April, 2017 − Rev. 5 1 2 3 1 YWW L1N 06CG CASE 369C DPAK STYLE 2 Y WW L1N06C G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION Device Package Shipping† MLD1N06CLT4 DPAK 2500 Tape & Reel DPAK (Pb−Free) 2500 Tape & Reel MLD1N06CLT4G °C D †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MLD1N06CL/D MLD1N06CL UNCLAMPED DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS Rating Single Pulse Drain−to−Source Avalanche Energy Starting TJ = 25°C Symbol Value Unit EAS 80 mJ ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 59 59 62 62 65 65 − − 0.6 6.0 5.0 20 − − 0.5 1.0 5.0 20 1.0 0.6 1.5 − 2.0 1.6 − − − − 0.63 0.59 1.1 1.0 0.75 0.75 1.9 1.8 − 1.1 1.5 2.0 1.1 2.3 1.3 2.75 1.8 gFS 1.0 1.4 − mhos td(on) − 1.2 2.0 ms tr − 4.0 6.0 td(off) − 4.0 6.0 tf − 3.0 5.0 − 4.5 − − 7.5 − OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (Internally Clamped) (ID = 20 mAdc, VGS = 0 Vdc) (ID = 20 mAdc, VGS = 0 Vdc, TJ = 150°C) Zero Gate Voltage Drain Current (VDS = 45 Vdc, VGS = 0 Vdc) (VDS = 45 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Source Leakage Current (VG = 5.0 Vdc, VDS = 0 Vdc) (VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150°C) IGSS Vdc mAdc mAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (ID = 250 mAdc, VDS = VGS) (ID = 250 mAdc, VDS = VGS, TJ = 150°C) VGS(th) Static Drain−to−Source On−Resistance (ID = 1.0 Adc, VGS = 4.0 Vdc) (ID = 1.0 Adc, VGS = 5.0 Vdc) (ID = 1.0 Adc, VGS = 4.0 Vdc, TJ = 150°C) (ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150°C) RDS(on) Static Source−to−Drain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc) VSD Static Drain Current Limit (VGS = 5.0 Vdc, VDS = 10 Vdc) (VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150°C) ID(lim) Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc) Vdc W Vdc Adc RESISTIVE SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS(on) = 5.0 Vdc, RGS = 50 W) Fall Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. www.onsemi.com 2 nH nH MLD1N06CL TJ = 25°C 3 10 V 6V 8V 4V 2 VGS = 3 V 1 0 VDS ≥ 7.5 V 4 ID , DRAIN CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) 4 -50°C 3 25°C 2 TJ = 150°C 1 0 0 2 4 6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 8 Figure 1. Output Characteristics 2 4 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8 Figure 2. Transfer Function THE CONCEPT SHORT CIRCUIT PROTECTION AND THE EFFECT OF TEMPERATURE From a standard power MOSFET process, several active and passive elements can be obtained that provide on−chip protection to the basic power device. Such elements require only a small increase in silicon area and/or the addition of one masking layer to the process. The resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. The device functions can now provide an economical alternative to smart power ICs for power applications requiring low on−resistance, high voltage and high current. These devices are designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high in−rush current or a shorted load condition could occur. The on−chip circuitry of the MLD1N06CL offers an integrated means of protecting the MOSFET component from high in−rush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an NPN transistor and integral resistors R1 and R2. R2 senses the current through the MOSFET and forward biases the NPN transistor’s base as the current increases. As the NPN turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the voltage across the gate−to−source of the power MOSFET and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3 A at 25°C to about 1.3 A at 150°C. Since the MLD1N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150°C. The metal current sense resistor R2 adds about 0.4 W to the power MOSFET’s on−resistance, but the effect of temperature on the combination is less than on a standard MOSFET due to the lower temperature coefficient of R2. The on−resistance variation with temperature for gate voltages of 4 and 5 V is shown in Figure 5. Back−to−back polysilicon diodes between gate and source provide ESD protection to greater than 2 kV, HBM. This on−chip protection feature eliminates the need for an external Zener diode for systems with potentially heavy line transients. OPERATION IN THE CURRENT LIMIT MODE The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage. Without some form of current limiting, a shorted load can raise a device’s junction temperature beyond the maximum rated operating temperature in only a few milliseconds. Even with no heatsink, the MLD1N06CL can withstand a shorted load powered by an automotive battery (10 to 14 V) for almost a second if its initial operating temperature is under 100°C. For longer periods of operation in the current−limited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the amount of heatsinking provided. www.onsemi.com 3 MLD1N06CL 4 VGS=5V VDS=7.5V R DS(on), ON-RESISTANCE (OHMS) ID(lim) , DRAIN CURRENT (AMPS) 4 3 2 1 3 2 25°C 0 50 100 TJ, JUNCTION TEMPERATURE (°C) TJ=-50°C 150°C 1 0 0 -50 ID = 1 A 150 0 2 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 Figure 4. RDS(on) Variation With Gate−To−Source Voltage Figure 3. ID(lim) Variation With Temperature 1.25 RDS(on), ON-RESISTANCE (OHMS) ID = 1 A 1 VGS = 4 V 0.75 VGS=5 V 0.5 0.25 -50 0 50 100 TJ, JUNCTION TEMPERATURE (°C) 150 BV(DSS) , DRAIN-SOURCE SUSTAINING VOLTAGE (VOLTS) WAS , SINGLE PULSE AVALANCHE ENERGY (mJ) Figure 5. On−Resistance Variation With Temperature 100 80 60 40 20 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 Figure 6. Single Pulse Avalanche Energy versus Junction Temperature 64 63 62 61 60 -50 www.onsemi.com 4 0 50 100 TJ, JUNCTION TEMPERATURE (°C) Figure 7. Drain−Source Sustaining Voltage Variation With Temperature 150 MLD1N06CL FORWARD BIASED SAFE OPERATING AREA (1.8 A at 150°C) and not the RDS(on). The maximum voltage can be calculated by the following equation: The FBSOA curves define the maximum drain−to−source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, “Transient Thermal Resistance − General Data and Its Use” provides detailed instructions. (150 − TA) ID(lim) (RqJC + RqCA) Vsupply = where the value of RqCA is determined by the heatsink that is being used in the application. DUTY CYCLE OPERATION When operating in the duty cycle mode, the maximum drain voltage can be increased. The maximum operating temperature is related to the duty cycle (DC) by the following equation: TC = (VDS x ID x DC x RqCA) + TA MAXIMUM DC VOLTAGE CONSIDERATIONS The maximum value of VDS applied when operating in a duty cycle mode can be approximated by: The maximum drain−to−source voltage that can be continuously applied across the MLD1N06CL when it is in current limit is a function of the power that must be dissipated. This power is determined by the maximum current limit at maximum rated operating temperature VDS = 150 − TC ID(lim) x DC x RqJC ID , DRAIN CURRENT (AMPS) 10 VGS = 10 V SINGLE PULSE TC = 25°C 10 ms 100 ms 1.0 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 dc 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100 Figure 8. Maximum Rated Forward Bias Safe Operating Area (MLD1N06CL) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 P(pk) 0.1 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) Figure 9. Thermal Response (MLD1N06CL) www.onsemi.com 5 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) 1.0E+00 1.0E+01 MLD1N06CL ton VDD RL toff td(on) Vout tr td(off) tf 90% Vin PULSE GENERATOR Rgen 90% DUT OUTPUT, Vout INVERTED z = 50 W 10% 50W 90% 50 W 50% INPUT, Vin Figure 10. Switching Test Circuit 50% PULSE WIDTH 10% Figure 11. Switching Waveforms ACTIVE CLAMPING MLD1N06CL, the integrated gate−to−source voltage elements provide greater than 2.0 kV electrostatic voltage protection. The avalanche voltage of the gate−to−drain voltage clamp is set less than that of the power MOSFET device. As soon as the drain−to−source voltage exceeds this avalanche voltage, the resulting gate−to−drain Zener current builds a gate voltage across the gate−to−source impedance, turning on the power device which then conducts the current. Since virtually all of the current is carried by the power device, the gate−to−drain voltage clamp element may be small in size. This technique of establishing a temperature compensated drain−to−source sustaining voltage (Figure 7) effectively removes the possibility of drain−to−source avalanche in the power device. The gate−to−drain voltage clamp technique is particularly useful for snubbing loads where the inductive energy would otherwise avalanche the power device. An improvement in ruggedness of at least four times has been observed when inductive energy is dissipated in the gate−to−drain clamped conduction mode rather than in the more stressful gate−to−source avalanche mode. The technology can provide on−chip realization of the popular gate−to−source and gate−to−drain Zener diode clamp elements. Until recently, such features have been implemented only with discrete components which consume board space and add system cost. The technology approach economically melds these features and the power chip with only a slight increase in chip area. In practice, back−to−back diode elements are formed in a polysilicon region monolithicly integrated with, but electrically isolated from, the main device structure. Each back−to−back diode element provides a temperature compensated voltage element of about 7.2 V. As the polysilicon region is formed on top of silicon dioxide, the diode elements are free from direct interaction with the conduction regions of the power device, thus eliminating parasitic electrical effects while maintaining excellent thermal coupling. To achieve high gate−to−drain clamp voltages, several voltage elements are strung together; the MLD1N06CL uses 8 such elements. Customarily, two voltage elements are used to provide a 14.4 V gate−to−source voltage clamp. For the TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS The MLD1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated load. No additional series gate resistance is required, but a 40 kW gate pulldown resistor is recommended to avoid a floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components. VBAT VDD D MCU G MLD1N06CL S www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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