MM74C905N

Revised July 2003 MM74C905 12-Bit Successive Approximation Register General Description Features The MM74C905 CMOS 12-bit successive approximation register contains all the digit control and storage necessary for successive approximation analog-to-digital conversion. Because of the unique capability of CMOS to switch to each supply rail without any offset voltage, it can also be used in digital systems as the control and storage element in repetitive routines. ■ Wide supply voltage range: 3.0V to 15V ■ Guaranteed noise margin: 1.0V ■ High noise immunity: 0.45 VCC (typ) ■ Low power TTL compatibility: Fan out of 2 driving 74L ■ Provision for register extension or truncation ■ Operates in START/STOP or continuous conversion mode ■ Drive ladder switches directly. For 10 bits or less with 50k/100k R/2R ladder network Ordering Code: Order Number MM74C905N Package Number N24A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide Connection Diagram Pin Assignments for DIP © 2003 Fairchild Semiconductor Corporation DS005910 www.fairchildsemi.com MM74C905 12-Bit Successive Approximation Register October 1987 MM74C905 Truth Table Time Inputs Outputs tn D S E D0 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 0 X L L X X X X X X X X X X X X X X 1 D11 H L X L H H H H H H H H H H H H 2 D10 H L D11 D11 L H H H H H H H H H H H 3 D9 H L D10 D11 D10 L H H H H H H H H H H 4 D8 H L D9 D11 D10 D9 L H H H H H H H H H 5 D7 H L D8 D11 D10 D9 D8 L H H H H H H H H 6 D6 H L D7 D11 D10 D9 D8 D7 L H H H H H H H 7 D5 H L D6 D11 D10 D9 D8 D7 D6 L H H H H H H 8 D4 H L D5 D11 D10 D9 D8 D7 D6 D5 L H H H H H 9 D3 H L D4 D11 D10 D9 D8 D7 D6 D5 D4 L H H H H 10 D2 H L D3 D11 D10 D9 D8 D7 D6 D5 D4 D3 L H H H 11 D1 H L D2 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 L H H 12 D0 H L D1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 L H 13 X H L D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 L 14 X X L X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 L X X H X H NC NC NC NC NC NC NC NC NC NC NC NC H = HIGH Level L = LOW Level X = Don’t Care NC = No Change www.fairchildsemi.com 2 CC MM74C905 Absolute Maximum Ratings(Note 1) Voltage at Any Pin Operating Temperature Range (TA) Storage Temperature Range (TS) −0.3V to VCC+0.3V −40°C to +85°C −65°C to +150°C Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Operating VCC Range 3.0V to 15V Absolute Maximum VCC Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. 16V Lead Temperature (TL) 260°C (Soldering, 10 seconds) DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5.0V 3.5 V VCC = 10V 8.0 V VCC = 5.0V 1.5 V VCC = 10V 2.0 V VCC = 5.0V, IO = −10 µA 4.5 VCC = 10V, IO = −10 µA 9.0 V V VCC = 5.0V, IO = 10 µA 0.5 VCC = 10V, IO = 10 µA 1.0 V 1.0 µA IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V ICC Supply Current VCC = 15V 0.005 −1.0 −0.005 0.05 V µA 300 µA CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VCC − 1.5 VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA VOUT(0) Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA V 0.8 V 0.4 V 2.4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) ISOURCE ISOURCE ISINK ISINK Output Source Current VCC = 5.0V, VOUT = 0V (P-Channel) TA = 25°C Output Source Current VCC = 10V, VOUT = 0V (P-Channel) TA = 25°C Output Sink Current VCC = 5.0V, VOUT = VCC (N-Channel) TA = 25°C Output Sink Current VCC = 10V, VOUT = VCC (N-Channel) TA = 25°C −1.75 −3.3 mA −8.0 −15 mA 1.75 3.6 mA 8.0 16 mA VCC = 10V ±5% RSOURCE Q11–Q0 Outputs VOUT = VCC − 0.3V 150 350 Ω 80 230 Ω TA = 25°C RSINK Q11–Q0 Outputs VCC = 10V ±5% VOUT = 0.3V TA = 25°C 3 www.fairchildsemi.com MM74C905 AC Electrical Characteristics (Note 2) TA = 25°C, CL = 50 pF, unless otherwise specified Symbol tpd Typ Max Propagation Delay Time from Parameter VCC = 5.0V Conditions Min 200 350 Units ns Clock Input to Outputs VCC = 10V 80 150 ns Propagation Delay Time from VCC = 5.0V 180 325 ns Clock Input to D0 (tpd(D0)) VCC = 10V 70 125 ns Propagation Delay Time from VCC = 5.0V 190 350 ns Register Enable (E) to Output VCC = 10V 75 150 ns Propagation Delay Time from VCC = 5.0V 190 350 ns Clock to CC (tpd(CC)) VCC = 10V 75 0.50 ns Data Input Set-Up Time VCC = 5.0V 80 ns VCC = 10V 30 ns (Q0–Q11) (tpd(Q)) tpd tpd (Q11) (tpd(E)) tpd tS tS tW tr, tf Start Input Set-Up Time Minimum Clock Pulse Width Maximum Clock Rise and Fall Time VCC = 5.0V 80 ns VCC = 10V 30 ns VCC = 5.0V 250 125 ns VCC = 10V 100 50 ns VCC = 5.0V 15 VCC = 10V 5.0 µs µs VCC = 5.0V 2.0 4.0 MHz VCC = 10V 5.0 10 MHz fMAX Maximum Clock Frequency CCK Clock Input Capacitance Clock Input (Note 3) 10 pF CIN Input Capacitance Any other Input (Note 3) 5 pF CPD Power Dissipation Capacitance (Note 4) 100 pF Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics Application Note— AN-90. Typical Performance Characteristics RSINK vs Temperature RSOURCE vs Temperature •These points are guaranteed by automatic testing. www.fairchildsemi.com •These points are guaranteed by automatic testing. 4 MM74C905 Timing Diagram 5 www.fairchildsemi.com MM74C905 Switching Time Waveforms USER NOTES FOR A/D CONVERSION LSB and using the complement of the MSB Q11 as the sign bit. The register can be used with either current switches that require a low voltage level to turn the switch ON or current switches that require a high voltage level to turn the switch ON. If current switches are used which turn ON with a low logic level, the resulting digit output from the register is active low. That is, a logic “1” is represented as a low voltage level. If current switches are used which turn ON with a high logic level, the resulting digit output is active high. A logic “1” is represented as a high voltage level. If the register is truncated and operated in the continuous conversion mode, a lock-up condition may occur on powerON. This situation can be overcome by making the START input the “OR” function of CC and the appropriate register output. The register, by suitable selection of register ladder network, can be used to perform either binary or BCD conversion. For a maximum error of ±½ LSB, the comparator must be biased. If current switches that require a high voltage level to turn ON are used, the comparator should be biased +½ LSB and if the current switches require a low logic level to turn ON, then the comparator must be biased −½ LSB. The register outputs can drive the 10 bits or less with 50k/ 100k R/2R ladder network directly for VCC = 10V or higher. In order to drive the 12-bit 50k/100k ladder network and have the ±½ LSB resolution, the MM74C902 or MM74C904 is used as buffers, three buffers for MSB (Q11), two buffers for Q10, and one buffer for Q9. The register can be used to perform 2's complement conversion by offsetting the comparator one half full range +½ www.fairchildsemi.com 6 MM74C905 Typical Applications 12-Bit Successive Approximation A-to-D Converter, Operating in Continuous 8–Bit Truncated Mode 12-Bit Successive Approximation A-to-D Converter, Operating in Continuous Mode, Drives the 50k/100k Ladder Network Directly Definition of Terms CP: Register clock input. Q11: True register MSB output. CC: Conversion complete—this output remains at VOUT(1) during a conversion and goes to VOUT(0) when conversion is complete. Q11: Complement of register MSB output. Qi (i = 0 to 11): Register outputs. S: Start input—holding start input at VIN(0) for at least one clock period will initiate a conversion by setting MSB (Q11) at VOUT(0) and all other output (Q10–Q0) at VOUT(1). If setup time requirements are met, a conversion may be initiated by holding start input at VIN(0) for less than one clock period. D: Serial data input—connected to comparator output in Ato-D applications. E: Register enable —this input is used to expand the length of the register. When E is at VIN(1) Q11 is forced to VOUT(1) and inhibits conversion. When not used for expansion E must be connected to VIN(0) (GND). DO: Serial data output—D input delayed by one clock period. 7 www.fairchildsemi.com MM74C905 12-Bit Successive Approximation Register Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide Package Number N24A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8