MM74HC02MTCX

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This literature is subject to all applicable copyright laws and is not for resale in any manner. MM74HC02 Quad 2-Input NOR Gate Features General Description • Typical Propagation Delay: 8 ns • Wide Power Supply Range: 2 V to 6 V • Low Quiescent Supply Current: 20 μA Maximum (74HC Series) The MM74HC02 NOR gates utilize advanced silicongate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. • Moisture Level Sensitivity 1 • Low Input Current: 1 μA Maximum • High Output Current: 4 mA Minimum Ordering Information Part Number Top Mark Package Packing Method MM74HC02M MM74HC02M SOIC 14L Rail MM74HC02MX MM74HC02M SOIC 14L Tape and Reel MM74HC02MTC HC02 TSSOP 14L Rail MM74HC02MTCX HC02 TSSOP 14L Tape and Reel All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Logic Diagram Pin Assignment for SOIC, TSSOP Top View © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 www.fairchildsemi.com MM74HC02 — Quad 2-Input NOR Gate March 2015 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7.0 V VIN DC Input Voltage -1.5 to VCC+1.5 V DC Output Voltage -0.5 to VCC+0.5 V VOUT IIK, IOK Clamp Diode Current ±20 mA IOUT DC Output Current, per pin ±25 mA ICC DC VCC or GND Current, per pin ±50 mA -65 to +150 °C TSTG Storage Temperature Range PD Power Dissipation TL Lead Temperature (Soldering 10 seconds) (2) 600 S.O. Package only 500 mW 260 °C Notes: 1. Unless otherwise specified all voltages are referenced to ground. 2. Power dissipation temperature derating - plastic “N” package: -12 mW/°C from 65°C to 85°C. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN, VOUT TA tr, tf Min. Max. Unit Supply Voltage Parameter 2 6 V DC Input or Output Voltage 0 VCC V 85 °C Operating Temperature Range Input Rise or Fall Times © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 -40 VCC = 2.0 V 1000 VCC = 4.5 V 500 VCC = 6.0 V 400 ns www.fairchildsemi.com 2 MM74HC02 — Quad 2-Input NOR Gate Absolute Maximum Ratings(1) Symbol Parameter VCC (V) Conditions TA = 25°C Typ. VIH VIL Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage 2.0 1.50 1.50 1.50 4.5 3.15 3.15 3.15 6.0 4.20 4.20 4.20 2.0 0.50 0.50 0.50 4.5 1.35 1.35 1.35 6.0 1.80 1.80 1.80 2.0 1.9 1.9 1.9 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 2.0 4.5 VOH Minimum HIGH Level Output Voltage 6.0 |IOUT| ≤ 20 μA VIN = VIL, |IOUT| ≤ 4.0 mA 4.20 3.98 3.84 3.70 6.0 VIN = VIL, |IOUT| ≤ 5.2 mA 5.70 5.48 5.34 5.20 4.5 Minimum LOW Level Output Voltage VIN = VIL, 4.5 2.0 VOL TA =-40 TA =-55 to 85°C to 125°C Unit Guaranteed Limits 6.0 VIN = VIH or VIL, |IOUT| ≤ 20 μA 0 0.1 0.1 0.1 0 0.1 0.1 0.1 0 0.1 0.1 0.1 4.5 VIN = VIH or VIL, |IOUT| ≤ 4.0 mA 0.20 0.26 0.33 0.40 6.0 VIN = VIH or VIL, |IOUT| ≤ 5.2 mA 0.20 0.26 0.33 0.40 V V V V IIN Maximum Input Current 6.0 VIN = VCC or GND ±0.1 ±0.1 ±0.1 μA ICC Maximum Quiescent Supply Current 6.0 VIN = VCC or GND IOUT = 0 μA 2.0 20 40 μA Note: 3. For a power supply of 5 V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5 V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5 V and 4.5 V respectively. (The VIH value at 5.5 V is 3.85 V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0 V values should be used. © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 www.fairchildsemi.com 3 MM74HC02 — Quad 2-Input NOR Gate DC Electrical Characteristics(3) VCC = 5 V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter Conditions tPHL, tPLH Maximum Propagation Delay Typ. Guaranteed Limit Unit 8 15 ns AC Electrical Characteristics VCC = 2.0 V to 6.0 V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter VCC (V) Conditions TA = 25°C Typ. tPHL, tPLH Maximum Propagation Delay tTLH, tTHL Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance(4) TA =-40 TA =-55 to 85°C to 125°C Unit Guaranteed Limits 2.0 45 90 113 134 4.5 9 18 23 27 6.0 8 15 19 23 2.0 30 75 95 110 4.5 8 15 19 22 6.0 7 13 16 19 (per gate) 20 Maximum Input Capacitance 5 ns ns pF 10 10 10 pF Note: 4. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 www.fairchildsemi.com 4 MM74HC02 — Quad 2-Input NOR Gate AC Electrical Characteristics 0.65 A 0.43TYP 14 8 B 6.4 6.10 3.2 1 PIN#1 IDENT 0.2 C B A 7 TOP VIEW 1.65 ALL LEAD TIPS 0.45 RECOMMENDED LAND PATTERN 1.2 MAX 0.30 0.19 ALL LEAD TIPS 0.1 C 0.65 SEE DETAIL A 0.90+0.15 -0.10 0.13 A B 0.20 0.09 C C FRONT VIEW 0.09 MIN NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 2009. E. LANDPATTERN STANDARD: SOP65P640X110-14M. F. DRAWING FILE NAME: MKT-MTC14rev7. GAGE PLANE 0.09 MIN 1.00 0.25 SEATING PLANE DETAIL A 8.75 8.50 A 7.62 14 8 14 B 0.65 8 4.00 3.80 6.00 1 PIN #1 IDENT. 1.27 (0.33) TOP VIEW 5.60 7 0.51 0.35 0.25 M C B A 1.75 MAX 1.70 1 1.27 LAND PATTERN RECOMMENDATION A C 1.50 1.25 FRONT VIEW 0.25 0.10 0.50 0.25 x 45 R0.10 GAGE PLANE R0.10 0.36 8° 0° 0.90 0.50 (1.04) 0.10 C 0.25 0.19 SIDE VIEW NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D. LAND PATTERN STANDARD: SOIC127P600X145-14M E. CONFORMS TO ASME Y14.5M, 2009 D. DRAWING FILENAME: MKT-M14Arev14 SEATING PLANE DETAIL A SCALE 16 : 1 7 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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