DATA SHEET
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Inverting Octal 3-STATE
Buffer
MM74HC240
SOIC−20 WB
CASE 751D−05
General Description
The MM74HC240 3−STATE buffer utilizes advanced silicon−gate
CMOS technology. It possesses high drive current outputs which
enable high speed operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power Schottky
devices, while retaining the advantage of CMOS circuitry, i.e., high
noise immunity and low power consumption. It has a fanout of 15
LS−TTL equivalent inputs.
The MM74HC240 is an inverting buffer and has two active LOW
enables (1G and 2G). Each enable independently controls 4 buffers.
All inputs are protected from damage due to static discharge by
diodes to VCC and ground.
Features
Typical Propagation Delay: 12 ns
3−STATE Outputs for Connection to System Buses
Wide Power Supply Range: 2–6 V
Low Quiescent Supply Current: 160 mA (74 Series)
Output Current: 6 mA
These are Pb−Free Devices
2A4
1Y8
2A3
1Y7
2A2
1Y6
2A1
1Y5
TSSOP−20 WB
CASE 948E
MARKING DIAGRAMS
20
20
HC
240A
ALYWG
G
HC240A
AWLYYWWG
1
1
(SOIC−20 WB)
(TSSOP−20 WB)
HC240A = Specific Device Code
A
= Assembly Location
L/WL
= Wafer Lot
Y/YY
= Year
W/WW
= Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
CONNECTION DIAGRAM
VCC
20
1
2G
1G
2G
1Y1
19
18
2A4
1Y2
17
2A3
16
1Y3 2A2
15
2
3
4
5
6
1A1
2Y4
1A2
2Y3
1A3
14
13
7
8
2Y2 1A4
1Y4
2A1
12
11
9
10
2Y1 GND
(Top View)
1A4
1Y4
1A3
1Y3
1A2
1Y2
TRUTH TABLE
1G
VCC
1Y
2G
2A
2Y
L
L
H
L
H
H
L
L
H
L
H
H
H
L
Z
H
H
Z
H
L
Z
H
H
Z
H = HIGH Level
L = LOW Level
Z = HIGH Impedance
1Y1
1A1
1A
ORDERING INFORMATION
1G
See detailed ordering, marking and shipping information in the
package dimensions section on page 4 of this data sheet.
Figure 1. Logic Diagram
Semiconductor Components Industries, LLC, 2005
November, 2022 − Rev. 1
1
Publication Order Number:
MM74HC240/D
MM74HC240
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
−0.5 to +7.0
V
DC Input Voltage
−0.5 to VCC + 0.5
V
DC Output Voltage
−0.5 to VCC + 0.5
V
Clamp Diode Current
20
mA
IOUT
DC Output Current, per Pin
35
mA
ICC
DC VCC or GND Current, per Pin
70
mA
−65 to +150
C
VCC
Supply Voltage
VIN
VOUT
IIK, IOK
TSTG
Storage Temperature Range
PD
Power Dissipation
(Note 2)
S. O. Package Only
600
500
TL
Lead Temperature (Soldering 10 seconds)
260
mW
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating − plastic “N” package: 12 mW/C from 65C to 85C.
RECOMMENDED OPERATIONG CONDITIONS (Note 1)
Symbol
Parameter
VCC
Supply Voltage
VIN, VOUT
DC Input or Output Voltage
TA
Operating Temperature Range
tr, tf
Input Rise or Fall Times
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Unit
2
6
V
0
VCC
V
−55
+125
C
−
−
−
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Note 3)
Symbol
Parameter
Conditions
TA = 25C
VCC
(V)
Typ
−40C TA 85C
−55C TA 125C
Guaranteed Limits
Unit
VIH
Minimum HIGH
Level Input Voltage
2.0
4.5
6.0
−
−
−
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum LOW
Level Input Voltage
2.0
4.5
6.0
−
−
−
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
VIN = VIH or VIL
Minimum HIGH
Level Output Voltage |IOUT| 20 mA
2.0
4.5
6.0
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN = VIH or VIL
|IOUT| 6.0 mA
|IOUT| 7.8 mA
4.5
6.0
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN = VIH or VIL
|IOUT| 6.0 mA
|IOUT| 7.8 mA
4.5
6.0
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
VIN = VCC or GND
6.0
−
0.1
1.0
1.0
VOL
IIN
VIN = VIH or VIL
Maximum LOW
Level Output Voltage |IOUT| 20 mA
Maximum Input
Current
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2
V
V
V
mA
MM74HC240
DC ELECTRICAL CHARACTERISTICS (Note 3) (continued)
Symbol
Parameter
Conditions
IOZ
Maximum 3−STATE
Output Leakage
Current
VIN = VIH or VIL
VOUT = VCC or GND
G = VIH, G = VIL
ICC
Maximum Quiescent VIN = VCC or GND
Supply Current
IOUT = 0 mA
TA = 25C
−40C TA 85C
−55C TA 125C
VCC
(V)
Typ
6.0
−
0.5
5
10
mA
6.0
−
8.0
80
160
mA
Guaranteed Limits
Unit
3. For a power supply of 5 V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5 V. Thus the 4.5 V values should be used
when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5 V and 4.5 V respectively. (The VIH value at 5.5 V is 3.85 V.) The
worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0 V values should be used.
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Unit
tPHL, tPLH
Maximum Propagation Delay
CL = 45 pF
12
18
ns
tPZH, tPZL
Maximum Enable Delay to Active Output
RL = 1 kW, CL = 45 pF
14
28
ns
tPHZ, tPLZ
Maximum Disable Delay from Active Output
RL = 1 kW, CL = 5 pF
13
25
ns
AC ELECTRICAL CHARACTERISTICS (VCC = 2.0 V to 6.0 V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified))
Symbol
tPHL,
tPLH
tPZH,
tPZL
Parameter
Maximum
Propagation Delay
Maximum Output
Enable Time
TA = 25C
−40C TA 85C
−55C TA 125C
VCC
(V)
Typ
CL = 50 pF
CL = 150 pF
2.0
2.0
55
80
100
150
126
190
149
224
ns
CL = 50 pF
CL = 150 pF
4.5
4.5
12
22
20
30
25
38
30
45
ns
CL = 50 pF
CL = 150 pF
6.0
6.0
11
28
17
26
21
32
25
38
ns
RL = 1 kW
CL = 50 pF
CL = 150 pF
2.0
2.0
75
100
150
200
189
252
224
298
CL = 50 pF
CL = 150 pF
4.5
4.5
15
20
30
40
38
50
45
60
ns
CL = 50 pF
CL = 150 pF
6.0
6.0
13
17
26
34
32
43
38
51
ns
RL = 1 kW
CL = 50 pF
2.0
4.5
6.0
75
15
13
150
30
26
189
38
32
224
45
38
ns
2.0
4.5
6.0
−
−
−
60
12
10
75
15
13
90
18
15
ns
−
−
12
50
−
−
−
−
−
−
Conditions
Guaranteed Limits
Unit
ns
tPHZ,
tPLZ
Maximum Output
Disable Time
tTLH,
tTHL
Maximum Output
Rise and Fall Time
CPD
Power Dissipation
Capacitance
(Note 4)
CIN
Maximum Input
Capacitance
−
5
10
10
10
pF
Maximum Output
Capacitance
−
10
20
20
20
pF
COUT
(per buffer)
G = VIH
G = VIL
pF
4. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
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3
MM74HC240
ORDERING INFORMATION
Device
Package
Shipping†
MM74HC240WM
SOIC−20 WB
(Pb−Free)
38 Units / Tube
MM74HC240WMX
SOIC−20 WB
(Pb−Free)
1000 Units / Tape & Reel
MM74HC240MTCX
TSSOP−20 WB
(Pb−Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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