MM74HC4040
12-Stage Binary Counter
tm
Features
General Description
■ Typical propagation delay: 16ns
The MM74HC4040 is a high speed binary ripple carry
counter. This counter is implemented utilizing advanced
silicon-gate CMOS technology to achieve speed performance similar to LS-TTL logic while retaining the low
power and high noise immunity of CMOS.
■ Wide operating voltage range: 2–6V
■ Low input current: 1µA Max.
■ Low quiescent current: 80µA Max. (74HC Series)
■ Output drive capability: 10 LS-TTL loads
The MM74HC4040 is a 12-stage counter. This device is
incremented on the falling edge (negative transition) of
the input clock, and all their outputs are reset to a low
level by applying a logical high on their reset input.
This device is pin equivalent to the CD4040. All inputs
are protected from damage due to static discharge by
protection diodes to VCC and ground.
Ordering Information
Order Number
MM74HC4040M(1)
MM74HC4040SJ(1)
MM74HC4040MTC(1)
MM74HC4040N
Package
Number
Package Description
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note:
1. Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
MM74HC4040 12-Stage Binary Counter
June 2007
MM74HC4040 12-Stage Binary Counter
Connection Diagram
Logic Diagram
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
VCC
Supply Voltage
VIN
DC Input Voltage
–1.5 to VCC +1.5V
DC Output Voltage
–0.5 to VCC +0.5V
VOUT
–0.5 to +7.0V
ICD
Clamp Diode Current
±20mA
IOUT
DC Output Current, per pin
±25mA
ICC
DC VCC or GND Current, per pin
±50mA
TSTG
PD
TL
Storage Temperature Range
–65°C to +150°C
Power Dissipation
Note 3
600mW
S.O. Package only
500mW
Lead Temperature (Soldering 10 seconds)
260°C
Note:
2. Unless otherwise specified all voltages are referenced to ground.
3. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VIN, VOUT
TA
tr , tf
Parameter
Min.
Max.
Units
Supply Voltage
2
6
V
DC Input or Output Voltage
0
VCC
V
–40
+85
°C
VCC = 2.0V
1000
ns
VCC = 4.5V
500
VCC = 6.0V
400
Operating Temperature Range
Input Rise and Fall Times
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
3
MM74HC4040 12-Stage Binary Counter
Absolute Maximum Ratings(2)
TA = –40
to 85°C
TA = 25°C
Symbol
VIH
VIL
VOH
Parameter
Conditions
VCC
Typ.
TA = –55
to 125°C
Guaranteed Limits
Units
Minimum HIGH Level
Input Voltage
2.0V
1.5
1.5
1.5
4.5V
3.15
3.15
3.15
6.0V
4.2
4.2
4.2
Maximum LOW Level
Input Voltage
2.0V
0.5
0.5
0.5
4.5V
1.35
1.35
1.35
6.0V
1.8
1.8
1.8
Minimum HIGH Level
Output Voltage
VIN = VIH or VIL:
V
V
V
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
4.5V
4.5
4.4
4.4
4.4
6.0V
6.0
5.9
5.9
5.9
|IOUT| ≤ 4.0mA
4.5V
4.2
3.98
3.84
3.7
|IOUT| ≤ 5.2mA
6.0V
5.7
5.48
5.34
5.2
2.0V
0
0.1
0.1
0.1
4.5V
0
0.1
0.1
0.1
6.0V
0
0.1
0.1
0.1
VIN = VIH or VIL:
VOL
Maximum LOW Level
Output Voltage
VIN = VIH or VIL:
V
|IOUT| ≤ 20 µA
VIN = VIH or VIL:
|IOUT| ≤ 4.0 mA
4.5V
0.2
.26
0.33
0.4
|IOUT| ≤ 5.2 mA
6.0V
0.2
.26
0.33
0.4
IIN
Maximum Input Current
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND,
IOUT = 0µA
6.0V
8.0
80
160
µA
Note:
4. For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V
respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15pF, tr = tf = 6ns
Symbol
fMAX
tPHL, tPLH
Parameter
Conditions
Maximum Operating Frequency
(5)
Guaranteed
Limit
Units
50
30
MHz
17
35
ns
tPHL
Maximum Propagation Delay Reset to any Q
16
40
ns
tREM
Minimum Reset Removal Time
10
20
ns
Minimum Pulse Width
10
16
ns
tW
Maximum Propagation Delay Clock to Q
Typ.
Note:
5. Typical Propagation delay time to any output can be calculated using: tP = 17 + 12(N–1) ns; where N is the number
of the output, QW, at VCC = 5V.
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
4
MM74HC4040 12-Stage Binary Counter
DC Electrical Characteristics(4)
VCC = 2.0V to 6.0V, CL = 50pF, tr = tf = 6ns (unless otherwise specified).
TA = –40
to 85°C
TA = 25°C
Symbol
fMAX
Parameter
Conditions
VCC
Typ
2.0V
10
6
5
4
4.5V
40
30
24
20
6.0V
50
35
28
24
2.0V
80
210
265
313
4.5V
21
42
53
63
6.0V
18
36
45
53
2.0V
80
125
156
188
4.5V
18
25
31
38
6.0V
15
21
26
31
Maximum Propagation
Delay Reset to any Q
(4020 and 4040)
2.0V
72
240
302
358
4.5V
24
48
60
72
6.0V
20
41
51
61
Minimum Reset Removal
Time
2.0V
100
126
149
4.5V
20
25
50
6.0V
16
21
25
2.0V
90
100
120
4.5V
16
20
24
6.0V
14
18
20
Maximum Operating
Frequency
tPHL, tPLH Maximum Propagation
Delay Clock to Q1
tPHL, tPLH Maximum Propagation
Delay Between Stages from
Qn to Qn+1
tPHL
tREM
tW
Minimum Pulse Width
tTLH, tTHL Maximum Output Rise and
Fall Time
tr , tf
TA = –55
to 125°C
Power Dissipation
Capacitance(6)
CIN
Maximum Input Capacitance
(per package)
Units
MHz
2.0V
30
75
95
110
4.5V
10
15
19
22
6.0V
9
13
16
19
1000
1000
1000
500
500
500
400
400
400
Maximum Input Rise and
Fall Time
CPD
Guaranteed Limits
55
5
ns
ns
ns
ns
ns
ns
ns
pF
10
10
10
pF
Note:
6. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC .
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
5
MM74HC4040 12-Stage Binary Counter
AC Electrical Characteristics
MM74HC4040 12-Stage Binary Counter
Timing Diagram
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
6
MM74HC4040 12-Stage Binary Counter
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
7
MM74HC4040 12-Stage Binary Counter
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
8
Dimensions are in millimeters unless otherwise noted.
5.00±0.10
4.55
5.90
4.45 7.35
0.65
4.4±0.1
1.45
5.00
0.11
12°
MTC16rev4
Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
9
MM74HC4040 12-Stage Binary Counter
Physical Dimensions (Continued)
MM74HC4040 12-Stage Binary Counter
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
10
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild semiconductor. The datasheet is printed for
reference information only.
Rev. I28
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
11
MM74HC4040 12-Stage Binary Counter
TRADEMARKS
