MM74HC574WM

MM74HC574 3-State Octal D-Type Edge-Triggered Flip-Flop The MM74HC574 high speed octal D−type flip−flops utilize advanced silicon−gate P−well CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS−TTL loads. Due to the large output drive capability and the 3−STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. These devices are positive edge triggered flip−flops. Data at the D inputs, meeting the set−up and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. www.onsemi.com SOP20 SJ SUFFIX CASE 565BG TSSOP20 MTC SUFFIX CASE 948AQ Features • • • • • • Typical Propagation Delay: 18 ns Wide Operating Voltage Range: 2 V – 6 V Low Input Current: 1 mA Maximum Low Quiescent Current: 80 mA Maximum Compatible with Bus−oriented Systems Output Drive Capability: 15 LS−TTL Loads PDIP20 N SUFFIX CASE 646AC MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Supply Voltage VCC −0.5 to + 7.0 V V DC Input Voltage VIN −1.5 to VCC + 1.5 V V VOUT −0.5 to VCC + 0.5 V V IIK, IOK ±20 mA IOUT ±35 mA ORDERING INFORMATION ICC ±70 mA See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. TSTG −65 to +150 °C Power Dissipation (Note 2) S.O. Package only PD 600 500 mW Lead Temperature (Soldering 10 s) TL 260 °C DC Output Voltage Clamp Diode Current DC Output Current, per pin DC VCC or GND Current, per pin Storage Temperature Range SOIC20 WM SUFFIX CASE 751BJ Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Unless otherwise specified all voltages are referenced to ground. 2. Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. © Semiconductor Components Industries, LLC, 1983 November, 2017 − Rev. 2 1 Publication Order Number: MM74HC574/D MM74HC574 ORDERING CODE Order Number Package Number Package Description MM74HC574WM M20B 20−Lead Small Outline Integrated Circuit (SOIC), JEDEC MS−013, 0.300″ Wide MM74HC574SJ M20D 20−Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3 mm Wide MM74HC574MTC MTC20 MM74HC574N N20A 20−Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO−153, 4.4 mm Wide 20−Lead Plastic Dual−In−Line Package (PDIP), JEDEC MS−001, 0.300″ Wide Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Output Clock Data Output L ↑ H H L ↑ L L L L X Q0 H X X Z Control H = HIGH Level L = LOW Level X = Don’t Care ↑ = Transition from Low−to−HIGH Z = High Impedance State Q0 = The level of the output before steady state input conditions were established Top View RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Characteristic Min Typ Max Units Supply Voltage 2 6 V DC Input or Output Voltage 0 VCC V −55 +125 °C 1000 500 400 ns TA Operating Temperature Range tr, tf Input Rise or Fall Times VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2 MM74HC574 DC ELECTRICAL CHARACTERISTICS (Note 3) TA = 255C TA = −55 to 1255C Guaranteed Limits Parameter VIH Minimum HIGH Level Input Voltage 2.0 V 4.5 V 6.0 V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum LOW Level Input Voltage 2.0 V 4.5 V 6.0 V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum HIGH Level Output Voltage V Maximum LOW Level Output Voltage VCC TA = −40 to 855C Symbol VOL Conditions Typ Units VIN = VIH or VIL ⎮IOUT⎜ ≤ 20 mA 2.0 V 4.5 V 6.0 V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 VIN = VIH or VIL ⎮IOUT⎜ ≤ 6.0 mA ⎮IOUT⎜ ≤ 7.8 mA 4.5 V 6.0 V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 VIN = VIH or VIL ⎮IOUT⎜ ≤ 20 mA 2.0 V 4.5 V 6.0 V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN = VIH or VIL ⎮IOUT⎜ ≤ 6.0 mA ⎮IOUT⎜ ≤ 7.8 mA 4.5 V 6.0 V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V V IIN Maximum Input Current VIN = VCC or GND 6.0 V ±0.1 ±1.0 ±1.0 mA IOZ Maximum 3−STATE Output Leakage Current VOUT = VCC or GND OC = VIH 6.0 V ±0.5 ±5.0 ±10 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 mA 6.0 V 8.0 80 160 mA Quiescent Supply Current per Input Pin VCC = 5.5 V VIN = 2.4 V or 0.4 V (Note 3) mA DICC OE 1.0 1.5 1.8 2.0 CLK 0.6 0.8 1.0 1.1 DATA 0.4 0.5 0.6 0.7 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. For a power supply of 5 V ±10% the worst−case output voltages (VOH, and VOL) occur for HC at 4.5 V. Thus the 4.5 V values should be used when designing with this supply. Worst−case VIH and VIL occur at VCC = 5.5 V and 4.5 V respectively. (The VIH value at 5.5 V is 3.85 V.) The worst−case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0 V values should be used. AC ELECTRICAL CHARACTERISTICS (VCC = 5 V, TA = 25°C, tr = tf = 6 ns) Symbol fMAX Parameter Conditions Maximum Operating Frequency Typ Guaranteed Limit Units 60 33 MHz tPHL, tPLH Maximum Propagation Delay, Clock to Q CL = 45 pF 17 27 ns tPZH, tPZL Maximum Output Enable Time RL = 1 kW, CL = 45 pF 19 28 ns tPHZ, tPLZ Maximum Output Disable Time RL = 1 kW, CL = 5 pF 14 25 ns tS Minimum Setup Time, Data to Clock 10 12 ns tH Minimum Hold Time, Clock to Data −3 5 ns tW Minimum Pulse Clock Width 8 15 ns www.onsemi.com 3 MM74HC574 AC ELECTRICAL CHARACTERISTICS (VCC = 2.0 − 6.0 V, CL = 50 pF, tr = tf = 6 ns unless otherwise specified) TA = 255C Symbol Parameter fMAX Maximum Operating Frequency CL = 50 pF 2.0 V 4.5 V 6.0 V tPHL, tPLH Maximum Propagation Delay, Clock to Q CL = 50 pF CL = 150 pF 2.0 V 2.0 V CL = 50 pF CL = 150 pF tPZH, tPZL tPHZ, tPLZ Maximum Output Enable Time Maximum Output Disable Time Conditions Typ VCC TA = −40 to 855C TA = −55 to 1255C Guaranteed Limits Units 33 30 35 28 24 28 23 20 23 MHz 18 51 30 155 38 194 45 233 ns 4.5 V 4.5 V 13 19 23 31 29 47 35 47 ns CL = 50 pF CL = 150 pF 6.0 V 6.0 V 12 18 20 27 25 34 30 41 ns RL = 1 kW CL = 50 pF CL = 150 pF 2.0 V 2.0 V 22 59 30 180 38 225 45 270 CL = 50 pF CL = 150 pF 4.5 V 4.5 V 14 20 28 36 35 45 42 54 ns CL = 50 pF CL = 150 pF 6.0 V 6.0 V 12 18 24 31 30 39 36 47 ns RL = 1 kW CL = 50 pF 2.0 V 4.5 V 6.0 V 15 12 10 30 25 21 38 31 27 45 38 32 ns ns tS Minimum Setup Time Data to Clock 2.0 V 4.5 V 6.0 V 6 12 20 17 15 25 21 18 30 25 ns tH Minimum Hold Time Clock to Data 2.0 V 4.5 V 6.0 V −1 5 0 0 6 0 0 8 0 0 ns tTHL, tTLH Maximum Output Rise and Fall Time 2.0 V 4.5 V 6.0 V 6 7 6 12 12 10 15 15 13 18 18 15 ns 30 9 8 15 16 14 20 20 18 24 24 20 ns 1000 500 400 1000 500 400 1000 500 400 ns CL = 50 pF tW Minimum Clock Pulse Width 2.0 V 4.5 V 6.0 V tr, tf Maximum Clock Input Rise and Fall Time 2.0 V 4.5 V 6.0 V CPD CIN COUT OC = VCC OC = GND 5 58 pF Maximum Input Capacitance 5 10 10 10 pF Maximum Output Capacitance 15 20 20 20 pF 4. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.onsemi.com 4 MM74HC574 PACKAGE DIMENSIONS SOP20 CASE 565BG ISSUE O www.onsemi.com 5 MM74HC574 PACKAGE DIMENSIONS TSSOP20, 4.4x6.5 CASE 948AQ−01 ISSUE A b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.50 6.60 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e L 0.65 BSC 0.45 L1 θ 0.60 0.75 1.00 REF 0º 8º e TOP VIEW D c A2 A θ1 L A1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. www.onsemi.com 6 L1 MM74HC574 PACKAGE DIMENSIONS PDIP−20, 300 mils CASE 646AC−01 ISSUE A E1 D TOP VIEW E A2 A c A1 e b1 b eB END VIEW SIDE VIEW NOM SYMBOL MIN A 3.56 A1 0.38 A2 2.92 3.30 4.95 MAX 5.33 b 0.36 0.45 0.55 b1 1.15 1.52 1.77 c 0.21 0.26 0.35 D 24.89 26.16 26.92 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e 2.54 BSC eB 7.88 L 2.99 10.92 3.30 L 3.81 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. www.onsemi.com 7 MM74HC574 PACKAGE DIMENSIONS SOIC−20, 300 mils CASE 751BJ−01 ISSUE O E1 SYMBOL MIN NOM MAX A 2.36 2.49 2.64 A1 0.10 A2 2.05 b 0.31 0.41 0.51 c 0.20 0.27 0.33 D 12.60 12.80 13.00 E 10.01 10.30 10.64 E1 7.40 7.50 7.60 E e PIN#1 IDENTIFICATION 2.55 1.27 BSC e b 0.30 0.75 h 0.25 L 0.40 θ 0º 8º θ1 5º 15º 0.81 1.27 TOP VIEW D h q1 q A2 A h q1 L A1 c END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. 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