MM74HC594N

Revised May 1999 MM74HC594 8-Bit Shift Register with Output Registers General Description This high speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clears are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features ■ Low quiescent current: 80 µA maximum ■ Low input current: 1 µA maximum ■ 8-bit serial-in, parallel-out shift register with storage ■ Wide operating voltage range: 2V to 6V ■ Cascadable ■ Shift register has direct clear ■ Guaranteed shift frequency: DC to30 MHz Ordering Code: Order Number Package Number Package Description MM74HC594M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC594N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK X X X L X X L X X ↑ SCLR RCLR H H Function Storage Register cleared Shift Register cleared Q’H = 0 Shift Register clocked QN = Qn−1, Q0 = SER Contents of Shift ↑ X H H Register transferred to output latches © 1999 Fairchild Semiconductor Corporation DS010915.prf www.fairchildsemi.com MM74HC594 8-Bit Shift Register with Output Registers January 1992 MM74HC594 Logic Diagram www.fairchildsemi.com 2 Recommended Operation Conditions Supply Voltage (VCC) −0.5 to +7.0V DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V ±20 mA Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) ±35 mA DC VCC or GND Current, per pin (ICC) ±70 mA Storage Temperature Range (TSTG) Min Max Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V −40 +85 °C (VIN, VOUT) Operating Temperature Range (TA) −65°C to +150°C Input Rise or Fall Times Power Dissipation (PD) (tr, tf) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) Units VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 260°C Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating—plastic “N” package: −12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = 25°C Typ TA = −40 to 85°C Guaranteed Limits 2.0V 1.5 1.5 Input Voltage 4.5V 3.15 3.15 6.0V 4.2 4.2 Maximum LOW Level 2.0V 0.5 0.5 Input Voltage 4.5V 1.35 1.35 6.0V 1.8 1.8 Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA QA thru QH 2.0V 2.0 1.9 1.9 4.5V 4.5 4.4 4.4 6.0V 6.0 5.9 5.9 |IOUT| ≤ 4.0 mA 4.5V 4.7 3.98 3.84 |IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 |IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 |IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 V V V V VIN = VIH or VIL VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA QA thru QH Units VIN = VIH or VIL Maximum LOW Level Q’H IIN VCC Conditions Minimum HIGH Level Q’H VOL (Note 4) 2.0V 0 0.1 0.1 4.5V 0 0.1 0.1 6.0V 0 0.1 0.1 |IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 V V VIN = VIH or VIL V VIN = VIH or VIL |IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 |IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 VIN = VCC or GND 6.0V ±0.1 ±1.0 µA Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 µA Supply Current IOUT = 0 µA Maximum Input V Current ICC Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC594 Absolute Maximum Ratings(Note 1) (Note 2) MM74HC594 AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating VCC Conditions CL = 50 pF Frequency tPHL, tPLH Maximum Propagation Delay CL = 50 pF from SCK to Q’H tPHL, tPLH tPHL, tPLH tPHL tS tR tS tW tr, tf tTHL, tTLH tTHL, tTLH 6 4.8 4.5V 30 24 6.0V 35 28 2.0V 150 185 4.5V 30 37 6.0V 25 31 CL = 50 pF 2.0V 150 185 CL = 150 pF 2.0V 200 250 CL = 50 pF 4.5V 30 37 CL = 150 pF 4.5V 40 50 CL = 50 pF 6.0V 25 31 CL = 150 pF 6.0V 34 43 Maximum Propagation Delay 2.0V 150 185 from SCLR to Q’H 4.5V 30 37 6.0V 25 31 2.0V 125 155 4.5V 25 31 6.0V 21 26 Maximum Propagation Delay CL = 50 pF SCLR LOW to RCK RCLR HIGH to SCK 2.0V 200 250 4.5V 40 50 6.0V 34 43 2.0V 50 63 4.5V 10 13 6.0V 9 11 2.0V 5 5 4.5V 5 5 6.0V 5 5 Minimum Setup Time 2.0V 90 110 from SER to SCK 4.5V 18 22 6.0V 15 19 Minimum Removal Time 2.0V 20 20 from SCLR to SCK 4.5V 10 10 6.0V 10 10 Minimum Setup Time 2.0V from SCK to RCK tH 2.0V from RCK to QA thru QH CL = 150 pF tS −40°C to +85°C 90 110 4.5V 18 22 6.0V 15 19 Minimum Hold Time 2.0V 5 5 SER to SCK 4.5V 5 5 6.0V 5 5 Minimum Pulse Width 2.0V 100 125 of SCK or SCLR or 4.5V 20 25 RCK or RCLR 6.0V 17 21 Maximum Input Rise and 2.0V 1000 1000 Fall Time, Clock 4.5V 500 500 6.0V 400 400 Maximum Output 2.0V 60 75 Rise and Fall Time 4.5V 12 15 QA - QH 6.0V 10 13 Maximum Output 2.0V 75 95 Rise and Fall Time 4.5V 15 19 Q’H 6.0V 13 16 www.fairchildsemi.com 4 Units Guaranteed Limits Maximum Propagation Delay from RCLR to QA thru QH tS TA = 25°C Typ MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol CPD Parameter (Continued) VCC Conditions Power Dissipation Capacitance, G = VCC Outputs Enabled (Note 5) TA = 25°C −40°C to +85°C Typ Units Guaranteed Limits 90 G = GND pF 150 CIN Maximum Input Capacitance 5 10 10 pF COUT Maximum Output Capacitance 15 20 20 pF Note 5: CPD determines the no load dynamic power consumption, and the no load dynamic current consumption. 5 www.fairchildsemi.com MM74HC594 AC Electrical Characteristics MM74HC594 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC594 8-Bit Shift Register with Output Registers Physical Dimensions inches (millimeters) unless otherwise noted (Continued)