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MM74HC595
8-Bit Shift Register with Output Latches
Features
Description
Low Quiescent current: 80µA Maximum
(74HC Series)
Low Input Current: 1µA Maximum
The MM74HC595 high-speed shift register utilizes
advanced silicon-gate CMOS technology. This device
possesses the high noise immunity and low power
consumption of standard CMOS integrated circuits, as
well as the ability to drive 15 LS-TTL loads.
Wide Operating Voltage Range: 2V–6V
8-Bit Serial-In, Parallel-Out Shift Register with
Storage
Cascadable
Shift Register has Direct Clear
Guaranteed Shift Frequency: DC to 30MHz
This device contains an eight-bit serial-in, parallel-out,
shift register that feeds an eight-bit D-type storage
register. The storage register has eight 3-state outputs.
Separate clocks are provided for both the shift register
and the storage register. The shift register has a directoverriding clear, serial input, and serial output
(standard) pins for cascading. Both the shift register
and storage register use positive-edge triggered clocks.
If both clocks are connected together, the shift register
state is one clock pulse ahead of the storage register.
The 74HC logic family is speed, function, and pin-out
compatible with the standard 74LS logic family. All
inputs are protected from damage due to static
discharge by internal diode clamps to VCC and ground.
Ordering Information
Operating
Temperature
Range
Eco
Status
MM74HC595M
-40 to +85°C
RoHS
MM74HC595MX
-40 to +85°C
RoHS
MM74HC595SJ
-40 to +85°C
RoHS
MM74HC595SJX
-40 to +85°C
RoHS
MM74HC595MTC
-40 to +85°C
RoHS
MM74HC595MTCX
-40 to +85°C
RoHS
Part Number
MM74HC595N
-40 to +85°C
RoHS
Package
Packing
Method
Tubes
16-Lead, Small Outline Integrated Circuit (SOIC),
JEDEC MS-012, 0.150 Inch Narrow
Tape and Reel
16-Lead, Small Outline Package (SOP), EIAJ
TYPE II, 5.3mm Wide
16-Lead, Thin Shrink Small Outline Package
(TSSOP), JEDEC MO-153, 4.4mm Wide
Tubes
Tape and Reel
Tubes
Tape and Reel
16-Lead, Plastic Dual In-Line Package (PDIP),
JEDEC MS-001, 0.300 Inch Wide
Tubes
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
MM74HC595 — 8-Bit Shift Register with Output Latches
June 2009
MM74HC595 — 8-Bit Shift Register with Output Latches
Block Diagram
Figure 1. Logic Diagram (Positive Logic)
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
2
MM74HC595 — 8-Bit Shift Register with Output Latches
Pin Configuration
Figure 2. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
QB
Output Bit B
2
QC
Output Bit C
3
QD
Output Bit D
4
QE
Output Bit E
5
QF
Output Bit F
6
QG
Output Bit G
7
QH
Output Bit H
8
GND
9
Q’H
Serial Data Output
10
SCLR
Shift Register Clear
Ground
11
SCK
Shift Register Clock Input
12
RCK
Storage Register Clock Input
13
G
14
SER
15
QA
Output Bit A
16
VCC
Supply Voltage
Output Enable
Serial Data Input
Truth Table
RCK
SCK
SCLR
G
Function
X
X
X
H
QA through QH = 3-state
X
X
L
L
Shift register clocked; Q’H = 0
X
↑
H
L
Shift register clocked; QN = Qn-1, Q0 = SER
↑
X
H
L
Contents of shift; register transferred to output latches
L = Logic Level LOW
H = Logic Level HIGH
X = Don’t Care
↑ = Transition from LOW to HIGH level
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC
VIN
VOUT
IIK, IOK
Parameter
Min.
Max.
Unit
-0.5
7.0
V
DC Input Voltage
-1.5 to VCC+
1.5
V
DC Output Voltage
-0.5 to VCC+
0.5
V
±20
mA
Supply Voltage
Clamp Diode Current
IOUT
DC Output Current, per Pin
±35
mA
ICC
DC VCC or GND Current, per Pin
±70
mA
+150
°C
TSTG
Storage Temperature Range
-65
(2)
PD
Power Dissipation
TL
Lead Temperature
ESD
Electrostatic Discharge Capability
PDIP
600
SOIC Package Only
500
Human Body Model,
JESD22-A114
mW
+260
°C
4000
V
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power dissipation temperature derating, plastic package (PDIP);12mW/°C from -65 to +85°C.
MM74HC595 — 8-Bit Shift Register with Output Latches
Absolute Maximum Ratings(1)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Supply Voltage
VIN, VOUT DC Input or Output Voltage
TA
tR,tF
Operating Temperature Range
Input Rise and Fall Times
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
Min.
Max.
Unit
2
6
V
0
VCC
V
+85
°C
-40
VCC=2.0V
1000
VCC=4.5V
500
VCC=6.0V
400
ns
www.fairchildsemi.com
4
Symbol
Parameter
Conditions
VCC
Typ.
VIH
VIL
VOH
Guaranteed Limits
Minimum HIGH
Level Input
Voltage
2.0V
1.50
1.50
1.50
4.5V
3.15
3.15
3.15
6.0V
4.20
4.20
4.20
Minimum LOW
Level Input
Voltage
2.0V
0.50
0.50
0.50
4.5V
1.35
1.35
1.35
6.0V
1.80
1.80
1.80
Minimum HIGH
Level Output
VIN=VIH or VIL
Voltage
2.0V
2.00
1.90
1.90
1.90
4.5V
4.50
4.40
4.40
4.40
6.0V
6.00
5.90
5.90
5.90
⏐IOUT⏐≤4.0mA
4.5V
4.20
3.98
3.84
3.70
⏐IOUT⏐≤5.2mA
6.0V
5.20
5.48
5.34
5.20
⏐IOUT⏐≤6.0mA
4.5V
4.20
3.98
3.84
3.70
⏐IOUT⏐≤7.8mA
6.0V
5.70
5.48
5.34
5.20
2.0V
0
0.10
0.10
0.10
4.5V
0
0.10
0.10
0.10
6.0V
0
0.10
0.10
0.10
⏐IOUT⏐≤4.0mA
4.5V
0.20
0.26
0.33
0.40
⏐IOUT⏐≤5.2mA
6.0V
0.20
0.26
0.33
0.40
⏐IOUT⏐≤6.0mA
4.5V
0.20
0.26
0.33
0.40
⏐IOUT⏐≤7.8mA
6.0V
0.20
0.26
0.33
0.40
6.0V
±0.1
±1.0
±1.0
µA
G=VIH
6.0V
±0.5
±5.0
±10
µA
IOUT=µA
6.0V
8.0
80
160
µA
Q’H
VIN=VIH or VIL
QA through QH
VIN=VIH or VIL
Minimum LOW
Level Output
VIN=VIH or VIL
Voltage
VOL
TA=-40 to TA=-55
85°C
to 125°C Units
TA=25°C
Q’H
VIN=VIH or VIL
QA through QH
VIN=VIH or VIL
⏐IOUT⏐≤20µA
⏐IOUT⏐≤20µA
IIN
Maximum Input
Output
VIN=VCC or GND
Leakage
IOZ
Maximum 3State Output
Leakage
ICC
VIN =VCC
Maximum
Quiescent
or GND
Supply Current
VOUT =VCC
or GND
V
V
V
V
V
V
MM74HC595 — 8-Bit Shift Register with Output Latches
Electrical Characteristics(3)
V
V
Note:
3. For a power supply of 5V ±10%, the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. The 4.5V
values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V,
respectively; VIH value at 5.5V is 3.85V. The worst-case leakage current (IIN, ICC, and IOZ) occurs for CMOS at
the higher voltage; so the 6.0V values should be used.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
5
VCC = 5V, TA = 25°C, tr = tf = 6ns.
Symbol
fMAX
Parameter
Conditions
Typ.
Guaranteed Limit
Units
MHz
Maximum Operating Frequency of SCK
50
30
Maximum Propagation Delay, SCK to Q’H
12
20
Maximum Propagation Delay, RCK to QA CL=45pF
thru Q’H
18
30
tPZH,tPZL
Maximum Output Enable Time from G to
QA thru Q’H
RL=1kΩ, CL=45pF
17
28
ns
tPHZ,tPLZ
Maximum Output Disable Time from G to
RL=1kΩ, CL=45pF
QA thru Q’H
15
25
ns
Minimum Setup Time from SER to SCK
20
ns
Minimum Setup Time from SCLR to SCK
20
ns
Minimum Setup Time from SER to
(4)
RCK
40
ns
tH
Minimum Hold Time from SER to SCK
0
ns
tW
Minimum Pulse Width of SCK or RCK
16
ns
tPHL,tPLH
tS
ns
Note:
4. This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be
connected together in which case the storage register state will be one clock pulse behind the shift register.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
MM74HC595 — 8-Bit Shift Register with Output Latches
AC Electrical Characteristics
www.fairchildsemi.com
6
VCC = 2.0−6.0V, CL = 50pF, tr = tf =6ns unless otherwise specified.
Symbol
Parameter
Conditions
VCC
Typ.
fMAX
Maximum Operating
Frequency
Maximum Propagation
Delay, SCK to Q’H
tPHL,tPLH
Maximum Propagation
Delay, RCK to QA thru Q’H
2.0V
CL=50pF
10.0
Maximum Output Disable
Time from G to QA thru Q’H
4.8
4.0
45.0
30.0
24.0
20.0
50.0
35.0
28.0
24.0
CL=50pF
2.0V
58.0
210.0
235.0
315.0
CL=150pF
2.0V
83.0
294.0
367.0
441.0
CL=50pF
4.5V
14.0
42.0
53.0
63.0
CL=150pF
4.5V
17.0
58.0
74.0
88.0
CL=50pF
6.0V
10.0
36.0
45.0
54.0
CL=150pF
6.0V
14.0
50.0
63.0
76.0
CL=50pF
2.0V
70.0
175.0
220.0
265.0
CL=150pF
2.0V
105.0 245.0
306.0
368.0
CL=50pF
4.5V
21.0
35.0
44.0
53.0
CL=150pF
4.5V
28.0
49.0
61.0
74.0
CL=50pF
6.0V
18.0
30.0
37.0
45.0
CL=150pF
6.0V
26.0
RL=1kΩ
tPHZ,tPLZ
6.0
6.0V
42.0
53.0
63.0
2.0V
175.0
221.0
261.0
4.5V
35.0
44.0
52.0
6.0V
Maximum Output Enable
Time from G to QA thru Q’H
Guaranteed Limits
4.5V
Maximum Propagation
Delay, SCLR to Q’H
tPZH,tPZL
TA=-40 to TA=-55
85°C
to 125°C Units
TA=25°C
30.0
37.0
44.0
CL=50pF
2.0V
75.0
175.0
220.0
265.0
CL=150pF
2.0V
100.0 245.0
306.0
368.0
CL=50pF
4.5V
15.0
35.0
44.0
53.0
CL=150pF
4.5V
20.0
49.0
61.0
74.0
CL=50pF
6.0V
13.0
30.0
37.0
45.0
CL=150pF
6.0V
17.0
42.0
53.0
63.0
2.0V
75.0
175.0
220.0
265.0
4.5V
15.0
35.0
44.0
53.0
6.0V
13.0
30.0
37.0
45.0
RL=1kΩ, CL=50pF
ns
ns
ns
MM74HC595 — 8-Bit Shift Register with Output Latches
Electrical Characteristics
ns
ns
ns
Continued on the following page…
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
7
VCC = 2.0−6.0V, CL = 50pF, tr = tf =6ns unless otherwise specified.
Symbol
Parameter
Conditions
VCC
Typ.
tS
tR
tS
tH
tW
tR,tF
Minimum Setup Time from
SER to SCK
RL=1kΩ, CL=50pF
Minimum Removal Time
from SCLR to SCK
Minimum Setup Time from
SCK to RCK
Minimum Hold Time from
SER to SCK
Maximum Input Rise and
Fall Time, Clock
tTHL,tTLH
Maximum Output Rise and
Fall Time Q’H
CPD
CIN
COUT
Power Dissipation
Capacitance, Outputs
(5)
Enabled
100
125
150
4.5V
20
25
30
6.0V
17
21
25
2.0V
50
63
75
4.5V
10
13
15
6.0V
9
11
13
2.0V
100
125
150
4.5V
20
25
30
6.0V
17
21
26
2.0V
5
5
5
4.5V
5
5
5
5
5
5
30
80
100
120
4.5V
9
16
20
24
6.0V
8
14
18
22
2.0V
1000
1000
1000
4.5V
500
500
500
400
400
400
2.0V
25
60
75
90
4.5V
7
12
15
18
6.0V
6
10
13
15
2.0V
75
95
110
4.5V
15
19
22
6.0V
13
16
19
G=VCC
90
G=GND
150
ns
ns
ns
ns
2.0V
6.0V
Maximum Output Rise and
Fall Time QA-QH
Guaranteed Limits
2.0V
6.0V
Minimum Pulse Width of
SCK or SCLR
TA=-40 to TA=-55
85°C
to 125°C Units
TA=25°C
ns
MM74HC595 — 8-Bit Shift Register with Output Latches
Electrical Characteristics
ns
ns
ns
pF
Maximum Input Capacitance
5
10
10
10
pF
Maximum Output
Capacitance
15
20
20
20
pF
Note:
2
5. CPD determines the no load dynamic power consumption, PD = CPD VCC f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCCf + ICC.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
8
MM74HC595 — 8-Bit Shift Register with Output Latches
Timing Diagram
Figure 3. Timing Diagram
Note:
6.
XXX
Implies that the output is in 3-state mode.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
9
10.00
9.80
A
8.89
16
9
B
4.00
3.80
6.00
PIN ONE
INDICATOR
1.75
1
5.6
8
0.51
0.35
1.27
(0.30)
0.25
M
1.27
C B A
0.65
LAND PATTERN RECOMMENDATION
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.10
C
0.25
0.19
MM74HC595 — 8-Bit Shift Register with Output Latches
Physical Dimensions
0.10 C
0.50
0.25 X 45°
(R0.10)
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE PLANE
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AC, ISSUE C.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD
FLASH AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-1994
E) LANDPATTERN STANDARD: SOIC127P600X175-16AM
F) DRAWING FILE NAME: M16AREV12.
(R0.10)
8°
0°
0.36
SEATING PLANE
0.90
0.50
(1.04)
DETAIL A
SCALE: 2:1
Figure 4. 16-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Inch Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
10
MM74HC595 — 8-Bit Shift Register with Output Latches
Physical Dimensions
Figure 5. 16-Lead, Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
11
5.00±0.10
4.55
5.90
4.45 7.35
4.4±0.1
0.65
1.45
5.00
0.11
MM74HC595 — 8-Bit Shift Register with Output Latches
Physical Dimensions
12°
MTC16rev4
Figure 6. 16-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
12
MM74HC595 — 8-Bit Shift Register with Output Latches
Physical Dimensions
19.68
18.66
16
A
9
6.60
6.09
1
8
(0.40)
TOP VIEW
0.38 MIN
5.33 MAX
8.13
7.62
3.42
3.17
3.81
2.92
2.54
15
0
0.35
0.20
0.58 A
0.35
1.78
1.14
8.69
17.78
SIDE VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-1994
E) DRAWING FILE NAME: N16EREV1
Figure 7. 16-Lead, Plastic Dual In-Line Package (PDIP), JEDEC MS-001, 0.300 Inch Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
13
MM74HC595 — 8-Bit Shift Register with Output Latches
© 1983 Fairchild Semiconductor Corporation
MM74HC595 • Rev. 1.0.2
www.fairchildsemi.com
14
ON Semiconductor and
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