MM74HCT164SJ

DATA SHEET www.onsemi.com 8-Bit Serial-in/Parallel-out Shift Register 14 1 MM74HCT164 SOIC−14 CASE 751EF Description The MM74HCT164 utilizes advanced silicon−gate CMOS technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices. This 8−bit shift register has gated serial inputs and CLEAR. Each register bit is a D−type master/slave flip−flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip−flop to the low level at the next clock pulse. A high level on one input enables the other input which will then determine the state of the first flip−flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8−bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HCT logic family is functionally as well as pin−out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug−in replacements for LS−TTL devices and can be used to reduce power consumption in existing designs. MARKING DIAGRAM 14 ZXYKK MM74HCT 164M 1 MM74HCT164M = Specific Device Code Z = Assembly Plant Code XY = Data Code (Year & Week) KK = Lot Traceability Code CONNECTION DIAGRAM Features • • • • • • Typical Propagation Delay: 20 ns Low Quiescent Current: 160 mA Maximum (74HCT Series) Low Input Current: 1 mA Maximum Fanout of 10 LS−TTL Loads TTL Input Compatible These are Pb−Free Devices (Top View) ORDERING INFORMATION Package Shipping† MM74HCT164M SOIC−14 (Pb−Free) 1100 Units / Tube MM74HCT164MX SOIC−14 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2002 November, 2022 − Rev. 1 1 Publication Order Number: MM74HCT164/D MM74HCT164 TRUTH TABLE Inputs Outputs Clear Clock A B QA QB L X X X L L L H L X X QAO QBO QHO H ↑ H H H QAn QGn H ↑ L X L QAn QGn H ↑ X L L QAn QGn … QH H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW−to−HIGH level QAO, QBO, QHO = the level of QA, QB, or QH, respectively, before the indicated steady state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicated a one−bit shift. Figure 1. Logic Diagram ABSOLUTE MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit −0.5 to +7.0 V VCC Supply Voltage VIN DC Input Voltage −0.5 to VCC + 0.5 V DC Output Voltage −0.5 to VCC + 0.5 V Clamp Diode Current ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC VCC or GND Current, per Pin ±50 mA −65 to +150 °C VOUT IIK, IOK TSTG Storage Temperature Range PD Power Dissipation S. O. Package Only 500 TL Lead Temperature (Soldering 10 seconds) 260 mW °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Unless otherwise specified all voltages are referenced to ground. www.onsemi.com 2 MM74HCT164 RECOMMENDED OPERATIONG CONDITIONS Symbol VCC VIN, VOUT Parameter Supply Voltage DC Input or Output Voltage TA Operating Temperature Range tr, tf Input Rise or Fall Times Min Max Unit 4.5 5.5 V 0 VCC V −55 +125 °C − 500 ns DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ±10% unless otherwise specified) TA = −405C TA = −555C to to 855C 1255C TA = 255C Symbol Parameter Typ Conditions Guaranteed Limits Unit VIH Minimum HIGH Level Input Voltage − 2.0 2.0 2.0 V VIL Maximum LOW Level Input Voltage − 0.8 0.8 0.8 V VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| = 20 mA |IOUT| = 4.0 mA, VCC = 4.5 V |IOUT| = 4.8 mA, VCC = 5.5 V VCC 4.2 5.2 VCC −0.1 3.98 4.98 VCC −0.1 3.84 4.84 VCC −0.1 3.7 4.7 Maximum LOW Level Voltage VIN = VIH or VIL |IOUT| = 20 mA |IOUT| = 4.0 mA, VCC = 4.5 V |IOUT| = 4.8 mA, VCC = 5.5 V 0 0.2 0.2 0.1 0.26 0.26 0.1 0.33 0.33 0.1 0.4 0.4 IIN Maximum Input Current VIN = VCC or GND − ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND, IOUT = 0 mA − 8.0 80 160 mA VIN = 2.4 V or 0.4 V (Note 2) − 1.0 1.3 1.5 mA VOL V V 2. This is measured per input pin. All other inputs are held at VCC or ground. AC ELECTRICAL CHARACTERISTICS (VCC = 5 V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns) Typ Guaranteed Limit Unit 55 35 MHz Maximum Propagation Delay, Clock to Q 17 27 ns tPHL Maximum Propagation Delay, from Clear to Q 23 38 ns tREM Minimum Removal Time, Clear to Clock 3 6 ns 13 ns Symbol fMAX tPHL, tPLH Parameter Conditions Maximum Operating Frequency from Clock to Q 50% Duty Cycle Clock tS Minimum Setup Time, Data to Clock tH ≥ 20 ns 6 tH Minimum Hold Time, Clock to Data tS ≥ 20 ns 1.5 5 ns tW Minimum Pulse Width, Preset or Clear 9 16 ns www.onsemi.com 3 MM74HCT164 AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, ±10%, CL = 50 pF, tr = tf = 6 ns unless otherwise specified) TA = 25°C Symbol fMAX Parameter Maximum Operating Frequency Conditions 50% Duty Cycle Clock TA −40°C to 85°C TA = −55°C to 125°C Typ Max Min Max Min Max Unit 45 30 − 25 − 22 MHz tPHL, tPLH Maximum Propagation Delay, from Clock to Q 20 30 − 38 − 45 ns tPHL Maximum Propagation Delay, from Clear to Q 26 41 − 51 − 61 ns tREM Minimum Removal Time, Clear to Clock 4 8 − 10 − 14 ns tS Minimum Setup Time, Data to Clock tH ≥ 20 ns 7 15 − 19 − 23 ns tH Minimum Hold Time, Clock to Data tS ≥ 20 ns 1.5 5 − 5 − 5 ns tW Minimum Pulse Width, Clock or Clear 10 18 − 22 − 27 ns tr, tf Maximum Input Rise and Fall Time − 500 − 500 − 500 ns Maximum Output Rise and Fall Time − 15 − 19 − 22 ns 160 − − − − − pF 5 10 − 10 − 10 pF tTLH, tTHL CPD Power Dissipation Capacitance (Note 3) CIN Maximum Input Capacitance 3. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC14 CASE 751EF ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13739G SOIC14 DATE 30 SEP 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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