DATA SHEET
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Inverting Octal 3-STATE
Buffer, Octal 3-STATE Buffer
MM74HCT240,
MM74HCT244
SOIC−20 WB
CASE 751D−05
TSSOP−20 WB
CASE 948E
TSSOP−20
CASE 948AQ
General Description
The MM74HCT240 and MM74HCT244 3−STATE buffers utilize
advanced silicon−gate CMOS technology and are general purpose
high speed inverting and non−inverting buffers. They possess high
drive current outputs which enable high speed operation even when
driving large bus capacitances. These circuits achieve speeds
comparable to low power Schottky devices, while retaining the low
power consumption of CMOS. All three devices are TTL input
compatible and have a fanout of 15 LS−TTL equivalent inputs.
MM74HCT devices are intended to interface between TTL and
NMOS components and standard CMOS devices. These parts are also
plug−in replacements for LS−TTL devices and can be used to reduce
power consumption in existing designs.
The MM74HCT240 is an inverting buffer and the MM74HCT244 is
a non−inverting buffer. Each device has two active low enables (1G
and 2G), and each enable independently controls 4 buffers.
All inputs are protected from damage due to static discharge by
diodes to VCC and ground.
MARKING DIAGRAMS
20
20
XXX
XXX
ALYWG
G
XXXXXX
AWLYYWWG
1
1
XXXXX = Specific Device Code
A
= Assembly Location
L/WL
= Wafer Lot
Y/YY
= Year
W/WW
= Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
CONNECTION DIAGRAMS
Pin Assignment for SOIC and TSSOP
Features
•
•
•
•
•
•
TTL Input Compatible
Typical Propagation Delay: 14 ns
3−STATE Outputs for Connection to System Buses
Low Quiescent Supply Current: 160 mA
High Output Drive Current: 6 mA (min)
These are Pb−Free Devices
TRUTH TABLES
MM74HCT240
MM74HCT240 (Top View)
1G
1A
1Y
2G
2A
2Y
L
L
H
L
L
H
L
H
L
L
H
L
H
L
Z
H
L
Z
H
H
Z
H
H
Z
1G
1A
1Y
2G
2A
2Y
L
L
L
L
L
L
MM74HCT244
L
H
H
L
H
H
H
L
Z
H
L
Z
H
H
Z
H
H
Z
ORDERING INFORMATION
NOTES: H = HIGH Level
L = LOW Level
Z = High Impedance
© Semiconductor Components Industries, LLC, 2005
November, 2022 − Rev. 2
MM74HCT244 (Top View)
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
1
Publication Order Number:
MM74HCT244/D
MM74HCT240, MM74HCT244
Logic Diagrams
MM74HCT240
MM74HCT244
Figure 1. Logic Diagrams
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2
MM74HCT240, MM74HCT244
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
−0.5 to +7.0
V
DC Input Voltage
−0.5 to VCC + 0.5
V
DC Output Voltage
−0.5 to VCC + 0.5
V
Clamp Diode Current
±20
mA
IOUT
DC Output Current, per Pin
±35
mA
ICC
DC VCC or GND Current, per Pin
±70
mA
−65 to +150
°C
VCC
Supply Voltage
VIN
VOUT
IIK, IOK
TSTG
Storage Temperature Range
PD
Power Dissipation
S. O. Package Only
500
TL
Lead Temperature (Soldering 10 seconds)
260
mW
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
RECOMMENDED OPERATING CONDITIONS (Note 1)
Symbol
Parameter
VCC
Supply Voltage
VIN, VOUT
DC Input or Output Voltage
TA
Operating Temperature Range
tr, tf
Input Rise or Fall Times
Min
Max
Unit
4.5
5.5
V
0
VCC
V
−55
+125
°C
−
500
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ±10% unless otherwise specified)
TA = 25°C
Symbol
Parameter
Typ
Conditions
TA = −40°C to 85°C
TA = −55°C to 125°C
Guaranteed Limits
Unit
VIH
Minimum HIGH
Level Input Voltage
−
2.0
2.0
2.0
V
VIL
Maximum LOW
Level Input Voltage
−
0.8
0.8
0.8
V
VOH
Minimum HIGH
VIN−EE = VIH or VIL
Level Output Voltage |IOUT| = 20 mA
|IOUT| = 6.0 mA, VCC = 4.5 V
|IOUT| = 7.2 mA, VCC = 5.5 V
VCC
4.2
5.2
VCC−0.1
3.98
4.98
VCC−0.1
3.84
4.84
VCC−0.1
3.7
4.7
VOL
Maximum LOW
VIN = VIH or VIL
Level Output Voltage |IOUT| = 20 mA
|IOUT| = 6.0 mA, VCC = 4.5 V
|IOUT| = 7.2 mA, VCC = 5.5 V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
IIN
Maximum Input
Current
VIN = VCC or GND, VIH or VIL
−
±0.05
±0.5
±1.0
mA
IOZ
Maximum 3−STATE
Output Leakage
Current
VOUT = VCC or GND
G = VIH
G = VIL
−
±0.25
±2.5
±10
mA
ICC
Maximum Quiescent VIN = VCC or GND
IOUT = 0 mA
Supply Current
−
4.0
40
160
mA
0.6
1.0
1.3
1.5
mA
VIN = 2.4 V or 0.5 V (Note 2)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Measured per input. All other inputs at VCC or GND.
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3
MM74HCT240, MM74HCT244
AC ELECTRICAL CHARACTERISTICS
(MM74HCT240, MM74HCT244 VCC = 5.0 V, tr = tf = 6 ns, TA = 25°C, unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Unit
tPHL, tPLH
Maximum Output Propagation Delay
CL = 45 pF
14
18
ns
tPZL, tPZH
Maximum Output Enable Time
CL = 45 pF, RL = 1 kW
20
30
ns
tPLZ, tPHZ
Maximum Output Disable Time
CL = 5 pF, RL = 1 kW
16
25
ns
AC ELECTRICAL CHARACTERISTICS
(MM74HCT240, MM74HCT244 VCC = 5.0 V ±10%, tr = tf = 6 ns, unless otherwise specified)
TA = 25°C
Symbol
Parameter
Conditions
Typ
TA = −40°C to 85°C
TA = −55°C to 125°C
Guaranteed Limits
Unit
tPHL,
tPLH
Maximum Output
Propagation Delay
CL = 50 pF
14
20
25
30
CL = 150 pF
20
28
35
42
tPZH,
tPZL
Maximum Output
Enable Time
RL = 1 kW, CL = 50 pF
21
30
38
45
ns
RL = 1 kW, CL = 150 pF
26
42
53
63
ns
tPHZ,
tPLZ
Maximum Output
Disable Time
RL = 1 kW
CL = 50 pF
16
25
32
38
ns
tTHL,
tTLH
Maximum Output
Rise and Fall Time
CL = 50 pF
6
12
15
18
ns
CIN
Maximum Input
Capacitance
10
15
15
15
pF
COUT
Maximum Output
Capacitance
15
20
20
20
pF
CPD
Power Dissipation
Capacitance
(Note 3)
5
90
−
−
−
−
−
−
(per buffer)
G = VCC, G = GND
G = GND, G = VCC
ns
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. CPD determines the no load dynamic power consumption, PD = CPD ⋅ VCC2 ⋅ f + ICC ⋅ VCC, and the no load dynamic current consumption,
IS = CPD ⋅ VCC ⋅ f + ICC.
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4
MM74HCT240, MM74HCT244
ORDERING INFORMATION
Device
Package
Shipping†
MM74HCT240MTCX
TSSOP−20, case 948AQ
(Pb−Free)
2500 Units / Tape & Reel
MM74HCT244MTC
TSSOP−20 WB, case 948E
(Pb−Free)
75 Units / Tube
MM74HCT244MTCX
TSSOP−20, case 948AQ
(Pb−Free)
2500 Units / Tape & Reel
MM74HCT244WM
SOIC−20 WB, case 751D−05
(Pb−Free)
38 Units / Tube
MM74HCT244WMX
SOIC−20 WB, case 751D−05
(Pb−Free)
1000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP20, 4.4x6.5
CASE 948AQ−01
ISSUE A
DATE 19 MAR 2009
b
SYMBOL
MIN
NOM
MAX
A
E1
E
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.50
6.60
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.65 BSC
e
L
0.45
0.75
1.00 REF
L1
θ
0.60
0º
8º
e
TOP VIEW
D
c
A2
A θ1
L
A1
SIDE VIEW
END VIEW
L1
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34453E
TSSOP20, 4.4X6.5
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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