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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
Revised May 2005
MM74HCT273
Octal D-Type Flip-Flop with Clear
General Description
Features
The MM74HCT273 utilizes advanced silicon-gate CMOS
technology. It has an input threshold and output drive similar to LS-TTL with the low standby power of CMOS.
■ Typical propagation delay: 20 ns
■ Low quiescent current: 80 PA maximum (74HCT series)
■ Fanout of 10 LS-TTL loads
These positive edge-triggered flip-flops have a common
clock and clear-independent Q outputs. Data on a D input,
having the specified set-up and hold time, is transferred to
the corresponding Q output on the positive-going transition
of the clock pulse. The asynchronous clear forces all outputs LOW when it is LOW.
All inputs to this device are protected from damage due to
electrostatic discharge by diodes to VCC and ground.
MM74HCT devices are intended to interface TTL and
NMOS components to CMOS components. These parts
can be used as plug-in replacements to reduce system
power consumption in existing designs.
Ordering Code:
Order Number
Package
Number
Package Description
MM74HCT273WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT273MTC
MM74HCT273N
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
© 2005 Fairchild Semiconductor Corporation
DS005760
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MM74HCT273 Octal D-Type Flip-Flop with Clear
February 1984
MM74HCT273
Truth Table
(Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
L
X
X
L
H
n
H
H
H
n
L
L
H
L
X
Q0
H HIGH Level (steady-state)
L LOW Level (steady-state)
X Don’t Care
n Transition from LOW-to-HIGH level
Q0 The level of Q before the indicated steady-state input
conditions were established.
Logic Diagram
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2
Q
Recommended Operating
Conditions
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per Pin (IOUT)
DC VCC or GND Current, per Pin (ICC)
Storage Temperature Range (TSTG)
0.5V to 7.0V
1.5V to VCC 1.5V
0.5V to VCC 0.5V
r20 mA
r25 mA
r50 mA
65qC to 150qC
Supply Voltage (VCC)
600 mW
S.O. Package only
500 mW
Max
Units
4.5
5.5
V
0
VCC
V
40
85
qC
500
ns
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
(tr, tf)
Power Dissipation (PD)
(Note 3)
Min
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power dissipation temperature derating—plastic “N” package: 12
mW/qC from 65qC to 85qC.
Lead Temperature (TL)
260qC
(Soldering, 10 seconds)
DC Electrical Characteristics
VCC
5V r 10% unless otherwise specified
Symbol
VIH
Parameter
TA
Conditions
25qC
Typ
Minimum HIGH Level
TA
40qC to 85qC TA 55qC to 125qC
Guaranteed Limits
Units
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Input Voltage
VIL
Maximum LOW Level
Input Voltage
VOH
Minimum HIGH Level
VIN
Output Voltage
|IOUT|
20 PA
VCC
VCC0.1
VCC0.1
VCC0.1
V
|IOUT|
4.0 mA, VCC
4.5V
4.2
3.98
3.84
3.7
V
4.8 mA, VCC
5.5V
5.2
4.98
4.84
4.7
V
|IOUT|
VOL
VIH or VIL
Minimum LOW Level
VIN
Voltage
|IOUT|
20 PA
0
0.1
0.1
0.1
V
|IOUT|
4.0 mA, VCC
4.5V
0.2
0.26
0.33
0.4
V
4.8 mA, VCC
5.5V
0.2
0.26
0.33
0.4
V
r0.1
r1.0
r1.0
PA
8
80
160
PA
0.6
0.8
0.9
mA
|IOUT|
VIH or VIL
IIN
Maximum Input
VIN
Current
VIH or VIL
ICC
Maximum Quiescent
VIN
Supply Current
IOUT
VIN
VCC or GND,
VCC or GND
0 PA
2.4V or 0.5V (Note 4)
Note 4: Measured per pin, all other inputs held at VCC or GND.
3
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MM74HCT273
Absolute Maximum Ratings(Note 1)
(Note 2)
MM74HCT273
AC Electrical Characteristics
VCC
5V, TA
25qC, CL
15 pF, tr
Symbol
tf 6 ns
Parameter
Conditions
Typ
Guaranteed
Limits
Units
fMAX
Maximum Operating Frequency
68
30
tPHL, tPLH
Maximum Propagation Delay from Clock to Q
18
30
MHz
ns
tPHL, tPLH
Maximum Propagation Delay from Clear to Q
21
30
ns
ns
tREM
Minimum Removal Time, Clear to Clock
1
5
tS
Minimum Set-Up Time D to Clock
6
20
ns
tH
Minimum Hold Time Clock to D
3
5
ns
tW
Minimum Pulse Width Clock or Clear
10
16
ns
AC Electrical Characteristics
VCC
5.0V r 10%, CL
Symbol
50 pF, tr
Parameter
tf 6 ns unless otherwise specified
Conditions
TA
25qC
Typ
fMAX
Maximum Operating
TA
40qC to 85qC TA 55qC to 125qC Units
Guaranteed Limits
68
27
21
18
MHz
22
37
46
56
ns
25
35
44
52
ns
1
5
6
7
ns
6
20
25
30
ns
3
5
5
5
ns
10
16
25
30
ns
500
500
500
ns
15
19
22
ns
Frequency
tPHL, tPLH Maximum Propagation
Delay from Clock to Q
tPHL, tPLH Maximum Propagation
Delay from Clear to Q
tREM
Minimum Removal
Time Clear to Clock
tS
Minimum Set-Up Time
D to Clock
tH
Minimum Hold Time
Clock to D
tW
Minimum Pulse Width
Clock or Clear
tr , tf
Maximum Input Rise
and Fall Time, Clock
tTHL, tTLH Maximum Output Rise
11
and Fall Time
CPD
Power Dissipation
(Per Flip-Flop)
50
pF
Capacitance (Note 5)
CIN
Maximum Input
6
10
10
10
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD
IS
CPD VCC2 f ICC VCC, and the no load dynamic current consumption,
CPD VCC2 f ICC.
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4
pF
MM74HCT273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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MM74HCT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
MM74HCT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
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MM74HCT273 Octal D-Type Flip-Flop with Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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www.fairchildsemi.com
8
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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