Revised February 1999
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The
MM74HCT373
octal
D-type
latches
and
MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply
range, but are LS-TTL input and output characteristic &
pin-out compatible. The 3-STATE outputs are capable of
driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and
ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
■ TTL input characteristic compatible
■ Typical propagation delay: 20 ns
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum
■ Compatible with bus-oriented systems
■ Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number
Package Number
MM74HCT373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373SJ
MM74HCT373MTC
MTC20
Package Descriptions
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N
N20A
MM74HCT373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC
MM74HCT373N
MTC20
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS005367.prf
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MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
February 1984
MM74HCT373 • MM74HCT374
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT373
Top View
MM74HCT374
MM74HCT373
MM74HCT374
Truth Tables
Output
LE
Data
Control
373
Output
Output
Control
Clock
Data
Output
(374)
L
H
H
H
L
↑
H
L
H
L
L
L
↑
L
L
L
L
X
Q0
L
L
X
Q0
H
X
X
Z
H
X
X
Z
H = HIGH Level
L = LOW Level
Q0 = Level of output before steady-state input conditions were established.
Z = High Impedance
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H
H = HIGH Level
L = LOW Level
X = Don’t Care
↑ = Transition from LOW-to-HIGH
Z = High Impedance State
Q0 = The level of the output before steady state input conditions were
established.
2
MM74HCT373 • MM74HCT374
Logic Diagrams
MM74HCT373
MM74HCT374
3
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MM74HCT373 • MM74HCT374
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
−0.5 to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN )
−1.5 to VCC +1.5V
DC Output Voltage (VOUT)
−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±35 mA
DC VCC or GND Current, per pin (ICC)
±70 mA
Storage Temperature Range (TSTG)
600 mW
500 mW
Units
V
0
VCC
V
−40
+85
°C
500
ns
Input Rise or Fall Times
(tr, tf)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
Lead Temperature (TL)
(Soldering 10 seconds)
5.5
(VIN, VOUT)
Operating Temperature Range (TA)
−65°C to +150°C
S.O. Package only
Max
4.5
DC Input or Output Voltage
Power Dissipation (PD)
(Note 3)
Min
Supply Voltage (VCC)
260°C
DC Electrical Characteristics
VCC = 5V ± 10% (unless otherwise specified)
Symbol
VIH
Parameter
TA = 25°C
Conditions
Typ
Minimum HIGH Level
TA = −40 to 85°C
TA = −55 to 125°C
Guaranteed Limits
Units
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Input Voltage
VIL
Maximum LOW Level
Input Voltage
VOH
VOL
IIN
IOZ
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT | = 20 µA
VCC
VCC− 0.1
VCC− 0.1
VCC− 0.1
V
|IOUT | = 6.0 mA, VCC = 4.5V
4.2
3.98
3.84
3.7
V
|IOUT | = 7.2 mA, VCC = 5.5V
5.7
4.98
4.84
4.7
V
Maximum LOW Level
VIN = VIH or VIL
Voltage
|IOUT | = 20 µA
Maximum Input
0
0.1
0.1
0.1
V
|IOUT | = 6.0 mA, VCC = 4.5V
0.2
0.26
0.33
0.4
V
|IOUT | = 7.2 mA, VCC = 5.5V
0.2
0.26
0.33
0.4
V
±0.1
±1.0
±1.0
µA
±0.5
±5.0
±10
µA
8.0
80
160
µA
1.0
1.3
1.5
mA
VIN = VCC or GND,
Current
VIH or VIL
Maximum 3-STATE
VOUT = VCC or GND
Output Leakage
Enable = V IH or VIL
Current
ICC
Maximum Quiescent
VIN = VCC or GND
Supply Current
IOUT = 0 µA
VIN = 2.4V or 0.5V (Note 4)
Note 4: Measured per pin. All others tied to VCCor ground.
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4
MM74HCT373: VCC = 5.0V, tr = tf = 6 ns TA = 25°C (unless otherwise specified)
Symbol
tPHL, tPLH
Parameter
Conditions
Guaranteed
Typ
Limit
Units
CL = 45 pF
18
25
ns
CL = 45 pF
21
30
ns
Maximum Enable Propagation Delay
CL = 45 pF
20
28
ns
Control to Output
RL = 1 kΩ
Maximum Disable Propagation Delay
CL = 5 pF
18
25
ns
Control to Output
RL = 1 kΩ
Maximum Propagation Delay
Data to Output
tPHL, tPLH
Maximum Propagation Delay
Latch Enable to Output
tPZH, tPZL
tPHZ, tPLZ
tW
Minimum Clock Pulse Width
16
ns
tS
Minimum Setup Time Data to Clock
5
ns
tH
Minimum Hold Time Clock to Data
10
ns
AC Electrical Characteristics
MM74HCT373: VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
tPHL, tPLH Maximum Propagation
Delay Data to Output
tPHL, tPLH Maximum Propagation Delay
Latch Enable to Output
tPZH, tPZL Maximum Enable Propagation
Delay Control to Output
TA=25°C
Conditions
TA=−40 to 85°C TA=−55 to 125°C
Typ
Guaranteed Limits
Units
CL = 50 pF
22
30
37
45
ns
CL = 150 pF
30
40
50
60
ns
CL = 50 pF
25
35
44
53
ns
CL = 150 pF
32
45
56
68
ns
CL = 50 pF
21
30
37
45
ns
CL = 150 pF
30
40
50
60
ns
21
30
37
45
ns
8
12
15
18
ns
RL = 1 kΩ
tPHZ, tPLZ Maximum Disable Propagation
Delay Control to Output
tTHL, tTLH Maximum Output Rise
CL = 50 pF
RL = 1 kΩ
CL = 50 pF
and Fall Time
tW
Minimum Clock Pulse Width
16
20
24
ns
tS
Minimum Setup Time Data to Clock
5
6
8
ns
tH
Minimum Hold Time Clock to Data
10
13
20
ns
CIN
Maximum Input Capacitance
10
10
10
pF
COUT
Maximum Output Capacitance
20
20
20
pF
CPD
Power Dissipation Capacitance
OC = VCC
5
pF
(Note 5)
OC = GND
52
pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
5
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MM74HCT373 • MM74HCT374
AC Electrical Characteristics
MM74HCT373 • MM74HCT374
AC Electrical Characteristics
MM74HCT374: VCC = 5.0V, tr = tf = 6 ns TA = 25°C (unless otherwise specified)
Symbol
Parameter
fMAX
Maximum Clock Frequency
tPHL, tPLH
Maximum Propagation Delay
Conditions
Typ
Guaranteed
Limit
Units
50
30
MHz
CL = 45 pF
20
32
ns
Maximum Enable Propagation Delay
CL = 45 pF
19
28
ns
Control to Output
RL = 1 kΩ
Maximum Disable Propagation Delay
CL = 5 pF
17
25
ns
Control to Output
RL = 1 kΩ
to Output
tPZH, tPZL
tPHZ, tPLZ
tW
Minimum Clock Pulse Width
20
ns
tS
Minimum Setup Time Data to Clock
5
ns
tH
Minimum Hold Time Clock to Data
16
ns
AC Electrical Characteristics
MM74HCT374: VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
TA = 25°C
Conditions
TA = −40 to 85°C TA = −55 to 125°C
Typ
fMAX
Maximum Clock Frequency
tPHL, tPLH Maximum Propagation Delay
to Output
tPZH, tPZL Maximum Enable Propagation
Delay Control to Output
Units
Guaranteed Limits
30
24
20
MHz
ns
CL = 50 pF
22
36
45
48
CL = 150 pF
30
46
57
69
ns
CL = 50 pF
21
30
37
45
ns
CL = 150 pF
30
40
50
60
ns
21
30
37
45
ns
8
12
15
18
ns
RL = 1 kΩ
tPHZ, tPLZ Maximum Disable Propagation
Delay Control to Output
tTHL, tTLH Maximum Output Rise
CL = 50 pF
RL = 1 kΩ
CL = 50 pF
and Fall Time
tW
Minimum Clock Pulse Width
16
20
24
ns
tS
Minimum Setup Time Data to Clock
20
25
30
ns
tH
Minimum Hold Time Clock to Data
5
5
5
ns
CIN
Maximum Input Capacitance
10
10
10
pF
COUT
Maximum Output Capacitance
20
20
20
pF
CPD
Power Dissipation Capacitance
OC = VCC
5
pF
(Note 6)
OC = GND
58
pF
Note 6: CPD determines the no load power consumption, PD = CPD V CC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + I CC.
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6
MM74HCT373 • MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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MM74HCT373 • MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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8
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
