MM80C97N

Revised January 1999 MM80C95 • MM80C97 • MM80C98 3-STATE Hex Buffers • 3-STATE Hex Inverters General Description Features The MM80C95, MM80C97 and MM80C98 gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. The MM80C95 and the MM80C97 convert CMOS or TTL outputs to 3-STATE outputs with no logic inversion, the MM80C98 provides the logical opposite of the input signal. The MM80C95 has common 3-STATE controls for all six devices. The MM80C97 and the MM80C98 have two 3-STATE controls; one for two devices and one for the other four devices. Inputs are protected from damage due to static discharge by diode clamps to VCC and GND. ■ Wide supply voltage range: 3.0V to 15V ■ Guaranteed noise margin: ■ High noise immunity: 1.0V 0.45 VCC (typ.) ■ TTL compatible: Drive 1 TTL Load Applications • Bus drivers: Typical propagation delay into 150 pF load is 40 ns Ordering Code: Order Number Package Number Package Description MM80C95N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM80C97M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM80C97N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM80C98N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP MM80C95 MM80C97 Top View Top View MM80C98 Top View © 1999 Fairchild Semiconductor Corporation DS005907.prf www.fairchildsemi.com MM80C95 • MM80C97 • MM80C98 3-STATE Hex Buffers • 3-STATE Hex Inverters October 1987 MM80C95 • MM80C97 • MM80C98 Schematic Diagrams Truth Tables MM80C95 MM80C95 3-STATE Disable Input DIS1 DIS2 Input Output 0 0 0 0 0 0 1 1 0 1 X H-z 1 0 X H-z 1 1 X H-z Disable Input Input Output DIS4 DIS2 0 0 0 0 0 0 1 1 X 1 X H-z (Note 1) 1 X X H-z (Note 2) Disable Input Input Output DIS4 DIS2 0 0 0 1 0 0 1 0 X 1 X H-z (Note 1) 1 X X H-z (Note 2) MM80C97 MM80C97 3-STATE MM80C98 MM80C98 3-STATE X = Irrelevant Note 1: Output 5–6 only Note 2: Output 1–4 only www.fairchildsemi.com 2 Power Supply Voltage (VCC) −0.3V to VCC + 0.3V Voltage at Any Pin Operating Temperature Range Storage Temperature Range (Soldering, 10 seconds) −40°C to +85°C −65°C to +150°C 700 mW Small Outline 500 mW 260°C Note 3: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Power Dissipation (PD) Dual-In-Line 18V Lead Temperature DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5V 3.5 V VCC = 10V 8.0 V VCC = 5V 1.5 V VCC = 10V 2.0 V VCC = 5V 4.5 V VCC = 10V 9.0 V VCC = 5V 0.5 V VCC = 10V 1.0 V 1.0 µA 1.0 µA VCC = 15V IIN(1) Logical “1” Input Current IIN(0) Logical “0” Input Current IOZ Output Current in High VCC = 15V, VO = 15V Impedance State VCC = 15V, VO = 0V Supply Current VCC = 15V ICC 0.005 −1.0 −0.005 0.005 −1.0 µA −0.005 0.01 µA 15 µA 0.8 V TTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VOUT(1) Logical “1” Output Voltage VCC = 4.75V, VCC − 1.5 V 2.4 V IO = −1.6 mA VOUT(0) Logical “0” Output Voltage VCC = 4.75V, 0.4 V IO = 1.6 mA OUTPUT DRIVE (Short Circuit Current) ISOURCE Output Source Current VCC = 5V, VIN(1) = 5V −4.35 mA −20 mA 4.35 mA 20 mA TA = 25°C, VOUT = 0V ISOURCE Output Source Current VCC = 10V, VIN(1) = 10V TA = 25°C, VOUT = 0V ISINK Output Sink Current VCC = 5V, VIN(0) = 0V TA = 25°C, VOUT = VCC ISINK Output Sink Current VCC = 10V, VIN(0) = 0V TA = 25°C, VOUT = VCC 3 www.fairchildsemi.com MM80C95 • MM80C97 • MM80C98 Absolute Maximum Ratings(Note 3) MM80C95 • MM80C97 • MM80C98 AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, unless otherwise noted. Symbol tpd0, tpd1 Parameter Conditions Min Typ Max Units VCC = 5V 60 100 ns VCC = 10V 25 40 ns Propagation Delay Time to a Logical “0” or Logical “1” from Data Input to Output MM80C95, MM80C97 MM80C98 tpd0, tpd1 VCC = 5V 70 150 ns VCC = 10V 35 75 ns ns Propagation Delay Time to a Logical “0” or Logical “1” from Data Input to Output MM80C95, MM80C97 MM80C98 t1H, t0H VCC = 5V, CL = 150 pF 85 160 VCC = 10V, CL = 150 pF 40 80 ns VCC = 5V, CL = 150 pF 95 210 ns VCC = 10V, CL = 150 pF 45 110 ns VCC = 5V 80 135 ns VCC = 10V 50 90 ns Delay from Disable Input to High Impedance RL = 10k, CL = 5 pF State, (from Logical “1” or Logical “0”) MM80C95 MM80C97 MM80C98 tH1, tH0 VCC = 5V 70 125 ns VCC = 10V 50 90 ns VCC = 5V 90 170 ns VCC = 10V 70 125 ns Delay from Disable Input to Logical “1” Level RL = 10k, CL = 50 pF (from High Impedance State) MM80C95 MM80C96 MM80C98 VCC = 5V 120 200 ns VCC = 10V 50 90 ns VCC = 5V 130 225 ns VCC = 10V 60 110 ns VCC = 5V 120 200 ns VCC = 10V 50 90 ns CIN Input Capacitance Any Input (Note 5) 5.0 pF COUT Output Capacitance 3-STATE Any Output (Note 5) 11 pF CPD Power Dissipation Capacitance (Note 6) 60 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Capacitance is guaranteed by periodic testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90. AC Test Circuits and Switching Time Waveforms www.fairchildsemi.com tpd0, tpd1 t1H and tH1 CMOS to CMOS t1H 4 tH1 t0H and tH0 MM80C95 • MM80C97 • MM80C98 AC Test Circuits and Switching Time Waveforms (Continued) t0H tH0 Note: Delays measured with input tr, tf ≤ 20 ns. Typical Performance Characteristics Propagation Delay vs Load Capacitance ∆tpd/pF vs Power Supply Voltage N-Channel Output Drive at 25°C P-Channel Output Drive at 25°C 5 www.fairchildsemi.com MM80C95 • MM80C97 • MM80C98 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM80C95 • MM80C97 • MM80C98 3-STATE Hex Buffers • 3-STATE Hex Inverters Physical Dimensions inches (millimeters) unless otherwise noted (Continued)