MMBFU310LT1G
JFET Transistor
N−Channel
Features
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
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Compliant
2 SOURCE
3
GATE
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Drain−Source Voltage
VDS
25
Vdc
Gate−Source Voltage
VGS
25
Vdc
IG
10
mAdc
Gate Current
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Thermal Resistance,
Junction−to−Ambient
Junction and Storage Temperature
3
SOT−23 (TO−236AB)
CASE 318−08
STYLE 10
1
2
THERMAL CHARACTERISTICS
Total Device Dissipation FR− 5 Board
(Note 1)
TA = 25°C
Derate above 25°C
1 DRAIN
PD
225
mW
1.8
mW/°C
RqJA
556
°C/W
TJ, Tstg
−55 to +150
°C
1. FR− 5 = 1.0 0.75 0.062 in.
MARKING DIAGRAM
M6C M G
G
1
M6C = Device Code
M = Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or overbar may
vary depending upon manufacturing location.
ORDERING INFORMATION
Device
MMBFU310LT1G
Package
Shipping†
SOT−23
(Pb−Free)
3000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 1994
October, 2016 − Rev. 6
1
Publication Order Number:
MMBFU310LT1/D
MMBFU310LT1G
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Min
Max
Unit
V(BR)GSS
−25
−
Vdc
Gate 1 Leakage Current − (VGS = −15 Vdc, VDS = 0)
IG1SS
−
−150
pA
Gate 2 Leakage Current − (VGS = −15 Vdc, VDS = 0, TA = 125°C)
IG2SS
−
−150
nAdc
VGS(off)
−2.5
−6.0
Vdc
IDSS
24
60
mAdc
VGS(f)
−
1.0
Vdc
Characteristic
OFF CHARACTERISTICS
Gate−Source Breakdown Voltage − (IG = −1.0 mAdc, VDS = 0)
Gate Source Cutoff Voltage − (VDS = 10 Vdc, ID = 1.0 nAdc)
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current − (VDS = 10 Vdc, VGS = 0)
Gate−Source Forward Voltage − (IG = 10 mAdc, VDS = 0)
SMALL−SIGNAL CHARACTERISTICS
Forward Transfer Admittance − (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz)
|Yfs|
10
18
mmhos
Output Admittance − (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz)
|yos|
−
250
mmhos
Input Capacitance − (VGS = −10 Vdc, VDS = 0 Vdc, f = 1.0 MHz)
Ciss
−
5.0
pF
Reverse Transfer Capacitance − (VGS = −10 Vdc, VDS = 0 Vdc, f = 1.0 MHz)
Crss
−
2.5
pF
60
I D , DRAIN CURRENT (mA)
60
VDS = 10 V
TA = -55°C
50
50
40
+25°C
IDSS
+25°C
40
30
20
10
-5.0
30
+150°C
20
+25°C
-55°C
10
+150°C
-1.0
-4.0
-3.0
-2.0
ID - VGS, GATE-SOURCE VOLTAGE (VOLTS)
IDSS - VGS, GATE-SOURCE CUTOFF VOLTAGE (VOLTS)
0
IDSS, SATURATION DRAIN CURRENT (mA)
70
70
0
Yfs , FORWARD TRANSCONDUCTANCE (mmhos)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
35
30
TA = -55°C
VDS = 10 V
f = 1.0 MHz
+25°C
25
20
+150°C
15
+25°C
-55°C
10
+150°C
5.0
0
5.0
4.0
3.0
2.0
1.0
VGS, GATE-SOURCE VOLTAGE (VOLTS)
Figure 1. Drain Current and Transfer
Characteristics vs Gate−Source Voltage
Figure 2. Forward Transconductance
vs Gate−Source Voltage
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2
0
10
1.0 k
10 k
100
VGS(off) = -2.3 V =
VGS(off) = -5.7 V =
1.0 k
Yos
10
RDS
CAPACITANCE (pF)
Yfs
Yfs
120
96
7.0
72
Cgs
4.0
48
24
Cgd
1.0
0
10
1.0
0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100
100
0.01
9.0
8.0
ID, DRAIN CURRENT (mA)
|S12|, |S22|
3.0
0.060 1.00
2.4
0.79 0.39
0.048 0.98
1.2
VDS = 10 V
ID = 10 mA
TA = 25°C
0.73 0.33
200
300
500
f, FREQUENCY (MHz)
0.024 0.94
S11
0.012 0.92
0.61 0.21
0.6
S12
700
0.55 0.15
100
1000
Figure 5. Common−Gate Y Parameter
Magnitude vs Frequency
q21, q11
180° 50°
q22
140°
10°
200
300
500
f, FREQUENCY (MHz)
q11, q12
-20° 120°
q21, q22
-40°
86°
-40° 100°
85°
-60°
80°
-120° 84°
-80°
60°
-100°
40°
-120°
20°
100
0
q11
-20°
q21
0.90
700 1000
Figure 6. Common−Gate S Parameter
Magnitude vs Frequency
q12, q22
-20° 87°
40°
0.036 0.96
0.67 0.27
Y12
20°
0
0
1.0
|S21|, |S11|
1.8
Y22
6.0
150°
2.0
0.85 0.45
Y12 (mmhos)
|Y11|, |Y21 |, |Y22 | (mmhos)
Y11
Y21
30°
3.0
S21
12
160°
4.0
S22
VDS = 10 V
ID = 10 mA
TA = 25°C
18
170°
5.0
VGS, GATE SOURCE VOLTAGE (VOLTS)
30
0
100
6.0
Figure 4. On Resistance and Junction
Capacitance vs Gate−Source Voltage
Figure 3. Common−Source Output Admittance
and Forward Transconductance vs Drain Current
24
7.0
q21
q22
-20°
-60°
-80°
-40°
-100°
q12
q11
130°
0°
100
-140°
VDS = 10 V
ID = 10 mA
TA = 25°C
200
300
500
f, FREQUENCY (MHz)
-60°
q12
-160° 83°
-180°
700
q21
-200° 82°
1000
Figure 7. Common−Gate Y Parameter
Phase−Angle vs Frequency
VDS = 10 V
ID = 10 mA
TA = 25°C
200
300
500
f, FREQUENCY (MHz)
q11
700
-80°
-100°
1000
Figure 8. S Parameter Phase−Angle
vs Frequency
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3
R DS , ON RESISTANCE (OHMS)
100 k
Yos, OUTPUT ADMITTANCE (μ mhos)
Yfs , FORWARD TRANSCONDUCTANCE (μmhos)
MMBFU310LT1G
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AS
DATE 30 JAN 2018
SCALE 4:1
D
0.25
3
E
1
2
T
HE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
DIM
A
A1
b
c
D
E
e
L
L1
HE
T
L
3X b
L1
VIEW C
e
TOP VIEW
A
A1
SIDE VIEW
SEE VIEW C
c
MIN
0.89
0.01
0.37
0.08
2.80
1.20
1.78
0.30
0.35
2.10
0°
MILLIMETERS
NOM
MAX
1.00
1.11
0.06
0.10
0.44
0.50
0.14
0.20
2.90
3.04
1.30
1.40
1.90
2.04
0.43
0.55
0.54
0.69
2.40
2.64
−−−
10 °
MIN
0.035
0.000
0.015
0.003
0.110
0.047
0.070
0.012
0.014
0.083
0°
INCHES
NOM
0.039
0.002
0.017
0.006
0.114
0.051
0.075
0.017
0.021
0.094
−−−
MAX
0.044
0.004
0.020
0.008
0.120
0.055
0.080
0.022
0.027
0.104
10°
GENERIC
MARKING DIAGRAM*
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT
XXXMG
G
1
3X
2.90
3X
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
0.90
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.95
PITCH
0.80
DIMENSIONS: MILLIMETERS
STYLE 1 THRU 5:
CANCELLED
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 7:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 9:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 11:
STYLE 12:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. CATHODE
3. CATHODE−ANODE
3. ANODE
STYLE 15:
PIN 1. GATE
2. CATHODE
3. ANODE
STYLE 16:
PIN 1. ANODE
2. CATHODE
3. CATHODE
STYLE 17:
PIN 1. NO CONNECTION
2. ANODE
3. CATHODE
STYLE 18:
STYLE 19:
STYLE 20:
PIN 1. NO CONNECTION PIN 1. CATHODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
2. ANODE
3. GATE
3. ANODE
3. CATHODE−ANODE
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 22:
PIN 1. RETURN
2. OUTPUT
3. INPUT
STYLE 23:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 24:
PIN 1. GATE
2. DRAIN
3. SOURCE
STYLE 27:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
STYLE 28:
PIN 1. ANODE
2. ANODE
3. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
STYLE 8:
PIN 1. ANODE
2. NO CONNECTION
3. CATHODE
STYLE 13:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 25:
PIN 1. ANODE
2. CATHODE
3. GATE
STYLE 14:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 26:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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