MMBT5087LT3

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MMBT5087LT1/D Low Noise Transistor PNP Silicon 1 BASE COLLECTOR 3 MMBT5087LT1 Motorola Preferred Device MAXIMUM RATINGS Rating Collector–Emitter Voltage Collector–Base Voltage Emitter–Base Voltage Collector Current — Continuous Symbol VCEO VCBO VEBO IC Value –50 –50 –3.0 –50 2 EMITTER Unit Vdc Vdc Vdc mAdc 1 2 3 CASE 318 – 08, STYLE 6 SOT– 23 (TO – 236AB) DEVICE MARKING MMBT5087LT1 = 2Q THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR-5 Board (1) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Total Device Dissipation Alumina Substrate, (2) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature Symbol PD Max 225 1.8 RθJA PD 556 300 2.4 RθJA TJ, Tstg 417 – 55 to +150 Unit mW mW/°C °C/W mW mW/°C °C/W °C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS Collector–Emitter Breakdown Voltage (IC = –1.0 mAdc, IB = 0) Collector–Base Breakdown Voltage (IC = –100 µAdc, IE = 0) Collector Cutoff Current (VCB = –10 Vdc, IE = 0) (VCB = –35 Vdc, IE = 0) 1. FR–5 = 1.0 x 0.75 x 0.062 in. 2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina V(BR)CEO V(BR)CBO ICBO — — –10 –50 –50 –50 — — Vdc Vdc nAdc Thermal Clad is a trademark of the Bergquist Company Preferred devices are Motorola recommended choices for future use and best overall value. Motorola Small–Signal Transistors, FETs and Diodes Device Data © Motorola, Inc. 1996 1 MMBT5087LT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued) Characteristic Symbol Min Max Unit ON CHARACTERISTICS DC Current Gain (IC = –100 µAdc, VCE = –5.0 Vdc) (IC = –1.0 mAdc, VCE = –5.0 Vdc) (IC = –10 mAdc, VCE = –5.0 Vdc) Collector–Emitter Saturation Voltage (IC = –10 mAdc, IB = –1.0 mAdc) Base–Emitter Saturation Voltage (IC = –10 mAdc, IB = –1.0 mAdc) hFE 250 250 250 VCE(sat) VBE(sat) — — 800 — — –0.3 0.85 Vdc Vdc — SMALL–SIGNAL CHARACTERISTICS Current–Gain — Bandwidth Product (IC = –500 µAdc, VCE = –5.0 Vdc, f = 20 MHz) Output Capacitance (VCB = –5.0 Vdc, IE = 0, f = 1.0 MHz) Small–Signal Current Gain (IC = –1.0 mAdc, VCE = –5.0 Vdc, f = 1.0 kHz) Noise Figure (IC = –20 mAdc, VCE = –5.0 Vdc, RS = 10 kΩ, f = 1.0 kHz) (IC = –100 µAdc, VCE = –5.0 Vdc, RS = 3.0 kΩ, f = 1.0 kHz) fT Cobo hfe NF — — 2.0 2.0 40 — 250 — 4.0 900 MHz pF — dB 2 Motorola Small–Signal Transistors, FETs and Diodes Device Data MMBT5087LT1 TYPICAL NOISE CHARACTERISTICS (VCE = – 5.0 Vdc, TA = 25°C) 10 7.0 en, NOISE VOLTAGE (nV) 5.0 IC = 10 µA 30 µA 3.0 2.0 1.0 mA 100 µA 300 µA BANDWIDTH = 1.0 Hz RS ≈ 0 In, NOISE CURRENT (pA) 1.0 7.0 5.0 3.0 2.0 1.0 0.7 0.5 0.3 0.2 1.0 10 20 50 100 200 500 1.0 k f, FREQUENCY (Hz) 2.0 k 5.0 k 10 k 0.1 10 20 50 100 200 500 1.0 k 2.0 k f, FREQUENCY (Hz) 5.0 k 10 k 300 µA 100 µA 30 µA 10 µA IC = 1.0 mA BANDWIDTH = 1.0 Hz RS ≈ ∞ Figure 1. Noise Voltage Figure 2. Noise Current NOISE FIGURE CONTOURS (VCE = – 5.0 Vdc, TA = 25°C) 1.0 M 500 k 200 k 100 k 50 k 20 k 10 k 5.0 k 2.0 k 1.0 k 500 200 100 10 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (µA) 0.5 dB 1.0 dB 2.0 dB 3.0 dB 5.0 dB 500 700 1.0 k 1.0 M 500 k 200 k 100 k 50 k 20 k 10 k 5.0 k 2.0 k 1.0 k 500 200 100 10 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (µA) BANDWIDTH = 1.0 Hz RS , SOURCE RESISTANCE (OHMS) RS , SOURCE RESISTANCE (OHMS) BANDWIDTH = 1.0 Hz 0.5 dB 1.0 dB 2.0 dB 3.0 dB 5.0 dB 500 700 1.0 k Figure 3. Narrow Band, 100 Hz Figure 4. Narrow Band, 1.0 kHz RS , SOURCE RESISTANCE (OHMS) 1.0 M 500 k 200 k 100 k 50 k 20 k 10 k 5.0 k 2.0 k 1.0 k 500 200 100 10 20 30 50 70 100 10 Hz to 15.7 kHz Noise Figure is Defined as: NF 0.5 dB 1.0 dB 2.0 dB 3.0 dB 5.0 dB 200 300 500 700 1.0 k IC, COLLECTOR CURRENT (µA) 4KTRS en = Noise Voltage of the Transistor referred to the input. (Figure 3) In = Noise Current of the Transistor referred to the input. (Figure 4) K = Boltzman’s Constant (1.38 x 10–23 j/°K) T = Temperature of the Source Resistance (°K) RS = Source Resistance (Ohms) + 20 log10 en2 ) 4KTRS ) In 2RS2 1 2 Figure 5. Wideband Motorola Small–Signal Transistors, FETs and Diodes Device Data 3 MMBT5087LT1 TYPICAL STATIC CHARACTERISTICS VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS) 1.0 100 IC, COLLECTOR CURRENT (mA) TA = 25°C 0.8 IC = 1.0 mA 10 mA 50 mA 100 mA TA = 25°C PULSE WIDTH = 300 µs 80 DUTY CYCLE ≤ 2.0% 300 µA 60 IB = 400 µA 350 µA 250 µA 200 µA 150 µA 0.6 0.4 40 100 µA 50 µA 0.2 20 0 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 IB, BASE CURRENT (mA) 0 5.0 10 20 0 5.0 10 15 20 25 30 35 VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) 40 Figure 6. Collector Saturation Region Figure 7. Collector Characteristics TJ = 25°C θV, TEMPERATURE COEFFICIENTS (mV/°C) 1.4 1.2 V, VOLTAGE (VOLTS) 1.0 0.8 1.6 *APPLIES for IC/IB ≤ hFE/2 0.8 *qVC for VCE(sat) 0 25°C to 125°C – 55°C to 25°C VBE(sat) @ IC/IB = 10 0.6 VBE(on) @ VCE = 1.0 V 0.4 0.2 VCE(sat) @ IC/IB = 10 0 0.1 0.2 0.5 1.0 2.0 5.0 10 20 IC, COLLECTOR CURRENT (mA) 50 100 0.8 25°C to 125°C 1.6 qVB for VBE 0.2 – 55°C to 25°C 2.4 0.1 0.5 1.0 2.0 5.0 10 20 IC, COLLECTOR CURRENT (mA) 50 100 Figure 8. “On” Voltages Figure 9. Temperature Coefficients 4 Motorola Small–Signal Transistors, FETs and Diodes Device Data MMBT5087LT1 TYPICAL DYNAMIC CHARACTERISTICS 500 300 200 100 70 50 30 20 td @ VBE(off) = 0.5 V 10 7.0 5.0 1.0 tr VCC = 3.0 V IC/IB = 10 TJ = 25°C t, TIME (ns) 1000 700 500 300 200 100 70 50 30 20 10 –1.0 ts VCC = – 3.0 V IC/IB = 10 IB1 = IB2 TJ = 25°C t, TIME (ns) tf 2.0 3.0 20 30 5.0 7.0 10 IC, COLLECTOR CURRENT (mA) 50 70 100 – 2.0 – 3.0 – 5.0 – 7.0 –10 – 20 – 30 IC, COLLECTOR CURRENT (mA) – 50 – 70 –100 Figure 10. Turn–On Time f T, CURRENT–GAIN — BANDWIDTH PRODUCT (MHz) Figure 11. Turn–Off Time 500 TJ = 25°C 300 200 VCE = 20 V 5.0 V C, CAPACITANCE (pF) 10 TJ = 25°C 7.0 Cib 5.0 3.0 2.0 Cob 100 70 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 1.0 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 IC, COLLECTOR CURRENT (mA) VR, REVERSE VOLTAGE (VOLTS) Figure 12. Current–Gain — Bandwidth Product Figure 13. Capacitance r(t) TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE P(pk) t1 t2 2.0 5.0 10 20 50 t, TIME (ms) 100 200 FIGURE 16 DUTY CYCLE, D = t1/t2 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 (SEE AN–569) ZθJA(t) = r(t) • RθJA TJ(pk) – TA = P(pk) ZθJA(t) 5.0 k 10 k 20 k 50 k 100 k 0.01 0.01 0.02 0.05 0.1 0.2 0.5 1.0 500 1.0 k 2.0 k Figure 14. Thermal Response Motorola Small–Signal Transistors, FETs and Diodes Device Data 5 MMBT5087LT1 104 VCC = 30 V IC, COLLECTOR CURRENT (nA) 103 102 101 100 10–1 10–2 ICEO DESIGN NOTE: USE OF THERMAL RESPONSE DATA A train of periodical power pulses can be represented by the model as shown in Figure 16. Using the model and the device thermal response the normalized effective transient thermal resistance of Figure 14 was calculated for various duty cycles. To find Z θJA(t), multiply the value obtained from Figure 14 by the steady state value RθJA. Example: Dissipating 2.0 watts peak under the following conditions: t1 = 1.0 ms, t2 = 5.0 ms (D = 0.2) Using Figure 14 at a pulse width of 1.0 ms and D = 0.2, the reading of r(t) is 0.22. The peak rise in junction temperature is therefore ∆T = r(t) x P(pk) x RθJA = 0.22 x 2.0 x 200 = 88°C. For more information, see AN–569. ICBO AND ICEX @ VBE(off) = 3.0 V –4 0 –2 0 0 + 20 + 40 + 60 + 80 + 100 + 120 + 140 + 160 TJ, JUNCTION TEMPERATURE (°C) Figure 15. Typical Collector Leakage Current 6 Motorola Small–Signal Transistors, FETs and Diodes Device Data MMBT5087LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T J(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad™. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. Motorola Small–Signal Transistors, FETs and Diodes Device Data 7 MMBT5087LT1 PACKAGE DIMENSIONS A L 3 BS 1 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0180 0.0236 0.0350 0.0401 0.0830 0.0984 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.45 0.60 0.89 1.02 2.10 2.50 0.45 0.60 V G C D H K J DIM A B C D G H J K L S V CASE 318–08 ISSUE AE SOT–23 (TO–236AB) STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR Motorola reserves the right to make changes without further notice to any products herein. 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