MMBT6520LT1

ON Semiconductort High Voltage Transistor PNP Silicon MMBT6520LT1 3 1 2 CASE 318–08, STYLE 6 SOT–23 (TO–236AF) MAXIMUM RATINGS Rating Collector–Emitter Voltage Collector–Base Voltage Emitter–Base Voltage Base Current Collector Current — Continuous Symbol VCEO VCBO VEBO IB IC Value –350 –350 –5.0 –250 –500 Unit Vdc Vdc Vdc mA mAdc 2 EMITTER 1 BASE COLLECTOR 3 DEVICE MARKING MMBT6520LT1 = 2Z THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR-5 Board (1) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Total Device Dissipation Alumina Substrate, (2) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature Symbol PD Max 225 1.8 RθJA PD 556 300 2.4 RθJA TJ, Tstg 417 –55 to +150 Unit mW mW/°C °C/W mW mW/°C °C/W °C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS Collector–Emitter Breakdown Voltage (IC = –1.0 mA) Collector–Base Breakdown Voltage (IC = –100 µA) Emitter–Base Breakdown Voltage (IE = –10 µA) Collector Cutoff Current (VCB = –250 V) Emitter Cutoff Current (VEB = –4.0 V) 1. FR–5 = 1.0 x 0.75 x 0.062 in. 2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina V(BR)CEO V(BR)CBO V(BR)EBO ICBO IEBO –350 –350 –5.0 — — — — — –50 –50 Vdc Vdc Vdc nA nA © Semiconductor Components Industries, LLC, 2001 1 November, 2001 – Rev. 2 Publication Order Number: MMBT6520LT1/D MMBT6520LT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued) Characteristic Symbol Min Max Unit ON CHARACTERISTICS DC Current Gain (IC = –1.0 mA, VCE = –10 V) (IC = –10 mA, VCE = –10 V) (IC = –30 mA, VCE = –10 V) (IC = –50 mA, VCE = –10 V) (IC = –100 mA, VCE = –10 V) Collector–Emitter Saturation Voltage (IC = –10 mA, IB = –1.0 mA) (IC = –20 mA, IB = –2.0 mA) (IC = –30 mA, IB = –3.0 mA) (IC = –50 mA, IB = –5.0 mA) Base–Emitter Saturation Voltage (IC = –10 mA, IB = –1.0 mA) (IC = –20 mA, IB = –2.0 mA) (IC = –30 mA, IB = –3.0 mA) Base–Emitter On Voltage (IC = –100 mA, VCE = –10 V) hFE 20 30 30 20 15 VCE(sat) — — — — VBE(sat) — — — VBE(on) — –0.75 –0.85 –0.90 –2.0 Vdc –0.30 –0.35 –0.50 –1.0 Vdc — — 200 200 — Vdc — SMALL–SIGNAL CHARACTERISTICS Current–Gain — Bandwidth Product (IC = –10 mA, VCE = –20 V, f = 20 MHz) Collector–Base Capacitance (VCB= –20 V, f = 1.0 MHz) Emitter–Base Capacitance (VEB= –0.5 V, f = 1.0 MHz) fT Ccb Ceb 40 — — 200 6.0 100 MHz pF pF http://onsemi.com 2 MMBT6520LT1 200 BANDWIDTH PRODUCT (MHz) VCE = 10 V TJ = 125°C 100 70 50 TJ = 25°C VCE = 20 V f = 20 MHz hFE, DC CURRENT GAIN 100 70 50 25°C -55°C 30 20 30 20 1.0 f T, CURRENT-GAIN 2.0 3.0 5.0 7.0 10 20 30 IC, COLLECTOR CURRENT (mA) 50 70 100 10 1.0 2.0 3.0 5.0 7.0 10 20 30 IC, COLLECTOR CURRENT (mA) 50 70 100 Figure 1. DC Current Gain Figure 2. Current–Gain — Bandwidth Product 1.2 V, VOLTAGE (VOLTS) 1.0 0.8 0.6 0.4 0.2 0 1.0 2.0 TJ = 25°C RθV, TEMPERATURE COEFFICIENTS (mV/°C) 1.4 2.5 2.0 1.5 1.0 0.5 0 IC + 10 IB 25°C to 125°C RθVC for VCE(sat) -55°C to 25°C -55°C to 125°C RθVB for VBE 2.0 3.0 5.0 7.0 10 20 30 IC, COLLECTOR CURRENT (mA) 50 70 100 VBE(sat) @ IC/IB = 10 VBE(on) @ VCE = 10 V -0.5 -1.0 -1.5 -2.0 -2.5 1.0 VCE(sat) @ IC/IB = 10 VCE(sat) @ IC/IB = 5.0 3.0 5.0 7.0 10 20 30 50 70 100 IC, COLLECTOR CURRENT (mA) Figure 3. “On” Voltages Figure 4. Temperature Coefficients 100 70 50 C, CAPACITANCE (pF) 30 20 10 7.0 5.0 3.0 2.0 1.0 0.2 0.5 TJ = 25°C Ceb t, TIME (ns) 1.0 k 700 500 300 200 100 70 50 30 20 td @ VBE(off) = 2.0 V VCE(off) = 100 V IC/IB = 5.0 TJ = 25°C tr Ccb 1.0 2.0 5.0 10 20 VR, REVERSE VOLTAGE (VOLTS) 50 100 200 10 1.0 2.0 3.0 5.0 7.0 10 20 30 IC, COLLECTOR CURRENT (mA) 50 70 100 Figure 5. Capacitance Figure 6. Turn–On Time http://onsemi.com 3 MMBT6520LT1 10 k 7.0 k 5.0 k 3.0 k t, TIME (ns) 2.0 k 1.0 k 700 500 300 200 100 1.0 2.0 3.0 5.0 7.0 10 20 30 IC, COLLECTOR CURRENT (mA) 50 70 100 tf VCE(off) = 100 V IC/IB = 5.0 IB1 = IB2 TJ = 25°C ts Figure 7. Turn–Off Time +VCC VCC ADJUSTED FOR VCE(off) = 100 V 1.0 k 2.2 k 20 k +10.8 V 50 Ω SAMPLING SCOPE 50 -9.2 V PULSE WIDTH ≈ 100 µs tr, tf ≤ 5.0 ns DUTY CYCLE ≤ 1.0% FOR PNP TEST CIRCUIT, REVERSE ALL VOLTAGE POLARITIES 1/2MSD7000 APPROXIMATELY -1.35 V (ADJUST FOR V(BE)off = 2.0 V) Figure 8. Switching Time Test Circuit r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 D = 0.5 0.2 SINGLE PULSE P(pk) SINGLE PULSE ZθJC(t) = r(t) • RθJC ZθJA(t) = r(t) • RθJA 0.2 0.5 1.0 2.0 5.0 10 20 50 t, TIME (ms) t1 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RθJC(t) 500 1.0 k 2.0 k 5.0 k 10 k 0.1 0.05 t2 DUTY CYCLE, D = t1/t2 100 200 Figure 9. Thermal Response http://onsemi.com 4 MMBT6520LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection 0.037 0.95 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA SOLDERING PRECAUTIONS The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad™. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 5 MMBT6520LT1 PACKAGE DIMENSIONS SOT–23 (TO–236) CASE 318–08 ISSUE AF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. A L 3 1 2 BS V G C D H K J DIM A B C D G H J K L S V INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0140 0.0285 0.0350 0.0401 0.0830 0.1039 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.35 0.69 0.89 1.02 2.10 2.64 0.45 0.60 STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR http://onsemi.com 6 MMBT6520LT1 Notes http://onsemi.com 7 MMBT6520LT1 Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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