MMFT2N02EL
Preferred Device
Power MOSFET
2 Amps, 20 Volts
N–Channel SOT–223
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. This device is also designed with
a low threshold voltage so it is fully enhanced with 5 Volts. This new
energy efficient device also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, dc–dc converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients. The device is housed in the SOT–223 package which is
designed for medium power surface mount applications.
• Silicon Gate for Fast Switching Speeds
• Low Drive Requirement to Interface Power Loads to Logic Level
ICs, VGS(th) = 2 Volts Max
• The SOT–223 Package can be Soldered Using Wave or Reflow. The
Formed Leads Absorb Thermal Stress During Soldering, Eliminating
the Possibility of Damage to the Die
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2 AMPERES
20 VOLTS
RDS(on) = 150 m
N–Channel
D
G
S
MARKING
DIAGRAM
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDS
20
Gate–to–Source Voltage – Continuous
VGS
±15
Drain Current – Continuous
Drain Current – Pulsed
ID
IDM
1.6
6.4
Adc
Total Power Dissipation @ TA = 25°C
Derate above 25°C
PD
(Note 1.)
0.8
6.4
Watts
mW/°C
Operating and Storage Temperature
Range
TJ, Tstg
–65 to
150
°C
EAS
66
mJ
RθJA
156
°C/W
260
°C
10
Sec
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 10 V, VGS = 5 V, Peak
IL= 2 A, L = 0.2 mH, RG = 25 Ω)
4
Vdc
1
2
TO–261AA
CASE 318E
STYLE 3
2N02L
LWW
3
L
WW
= Location Code
= Work Week
PIN ASSIGNMENT
4 Drain
THERMAL CHARACTERISTICS
Thermal Resistance –
Junction–to–Ambient (surface mounted)
Maximum Temperature for Soldering
Purposes,
Time in Solder Bath
1
Gate
2
Drain
3
Source
TL
1. Power rating when mounted on FR–4 glass epoxy printed circuit board using
recommended footprint.
ORDERING INFORMATION
Device
Package
MMFT2N02ELT1
SOT–223
Shipping
1000 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2000
November, 2000 – Rev. 4
1
Publication Order Number:
MMFT2N02EL/D
MMFT2N02EL
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
V(BR)DSS
20
–
–
Vdc
Zero Gate Voltage Drain Current, (VDS = 20 V, VGS = 0)
IDSS
–
–
10
µAdc
Gate–Body Leakage Current, (VGS = 15 V, VDS = 0)
IGSS
–
–
100
nAdc
Gate Threshold Voltage, (VDS = VGS, ID = 1 mA)
VGS(th)
1
–
2
Vdc
Static Drain–to–Source On–Resistance, (VGS = 5 V, ID = 0.8 A)
RDS(on)
–
–
0.15
Ohms
Drain–to–Source On–Voltage, (VGS = 5 V, ID = 1.6 A)
VDS(on)
–
–
0.32
Vdc
Forward Transconductance, (VDS = 10 V, ID = 0.8 A)
gFS
–
2.6
–
mhos
Ciss
–
580
–
Coss
–
430
–
Crss
–
250
–
td(on)
–
16
–
tr
–
73
–
td(off)
–
77
–
tf
–
107
–
Qg
–
20
–
Qgs
–
1.7
–
Qgd
–
6
–
VSD
–
0.9
–
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage, (VGS = 0, ID = 250 µA)
ON CHARACTERISTICS
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 15 V,
VGS = 0,
f = 1 MH
MHz))
pF
SWITCHING CHARACTERISTICS
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 15 V, ID = 1.6 A
VGS = 5 V
V, RG = 50 ohms
ohms,
RGS = 25 ohms)
Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
(VDS = 16 V, ID = 1.6 A,
VGS = 5 Vdc)
S Fi
See
Figures 15 and
d 16
ns
nC
SOURCE DRAIN DIODE CHARACTERISTICS (Note 2.)
Forward On–Voltage
IS = 1.6 A, VGS = 0
IS = 1.6 A, VGS = 0,
dlS/dt = 400 A/µs,
A/µs
Reverse Recovery Time
VR = 16 V
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%
Forward Turn–On Time
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2
ton
trr
Vdc
Limited by stray inductance
–
55
–
ns
MMFT2N02EL
TYPICAL ELECTRICAL CHARACTERISTICS
I D, DRAIN CURRENT (AMPS)
7
10
6
5
1.2
TJ = 25°C
4.5
8
4
6
3.5
4
3
2
0
VGS(TH), GATE THRESHOLD VOLTAGE
(NORMALIZED)
10
VGS = 2.5 V
0
1
2
3
4
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VDS = VGS
ID = 1 mA
1.1
1
0.9
0.8
0.7
-50
5
I D, DRAIN CURRENT (AMPS)
8
TJ = -55°C
25°C
6
VDS = 8 V
150
0.3
VGS = 5 V
0.25
100°C
4
0.2
TJ = 100°C
0.15
2
25°C
0.1
-55°C
0.05
0
0
2
4
6
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
7
0
0
0.5
TJ = 25°C
ID = 1.6 A
0.4
0.3
0.2
0.1
0
2
3
4
5
6
7
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
1
2
3
ID, DRAIN CURRENT (AMPS)
4
Figure 4. On–Resistance versus Drain Current
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 3. Transfer Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
50
100
TJ, JUNCTION TEMP (°C)
Figure 2. Gate–Threshold Voltage Variation
With Temperature
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 1. On Region Characteristics
0
8
0.5
0.4
VGS = 5 V
ID = 1.6 A
0.3
0.2
0.1
0
-50
Figure 5. On–Resistance versus
Gate–to–Source Voltage
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. On–Resistance versus Junction
Temperature
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3
150
MMFT2N02EL
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on an ambient temperature of
25°C and a maximum junction temperature of 150°C.
Limitations for repetitive pulses at various ambient
temperatures can be determined by using the thermal
response curves. ON Semiconductor Application Note,
AN569, “Transient Thermal Resistance–General Data and
Its Use” provides detailed instructions.
I D, DRAIN CURRENT (AMPS)
10
r(t), EFFECTIVE THERMAL RESISTANCE
(NORMALIZED)
1
100
20ms
ms
1s
DC
0.1
500ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current,
IDM and the breakdown voltage, BVDSS. The switching SOA
is applicable for both turn–on and turn–off of the devices for
switching times less than one microsecond.
1.0
VGS = 15 V
SINGLE PULSE
TA = 25°C
1
10
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
D = 0.5
0.2
0.1
0.01
0.001
1.0E-05
0.1
0.05
P(pk)
0.02
0.01
t1
SINGLE PULSE
1.0E-04
1.0E-03
RθJA(t) = r(t) RθJA
RθJA = 156°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TA = P(pk) RθJA(t)
t2
DUTY CYCLE, D = t1/t2
1.0E-02
t, TIME (s)
1.0E-01
1.0E+00
1.0E+01
Figure 8. Thermal Response
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated
source–drain current versus re–applied drain voltage when the source–drain diode has undergone forward bias. The curve shows
the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to
those of Figure 9 are present. Full or half–bridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device,
package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse
blocking.
VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; IFM is the maximum forward
source–drain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in ON Semiconductor’s test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns
was attained with dI S /dt of 400 A/µs.
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4
MMFT2N02EL
15 V
0
VGS
IFM
dlS/dt
90%
IS
10%
trr
ton
IRM
0.25 IRM
tfrr
VDS(pk)
VR
VDS
Vf
VdsL
MAX. CSOA
STRESS AREA
Figure 9. Commutating Waveforms
10
RGS
IS , SOURCE CURRENT (AMPS)
9
DUT
8
dIS/dt ≤ 400 A/µs
7
-
6
VR
+
5
IFM
IS
VDS
4
+
3
20 V
-
2
VGS
1
0
0
2
4
6
8
Li
VR = 80% OF RATED VDSS
VdsL = Vf + Li ⋅ dlS/dt
10 12 14 16 18 20 22 24 26 28 30
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 10. Commutating Safe Operating Area (CSOA)
Figure 11. Commutating Safe Operating Area
Test Circuit
BVDSS
L
VDS
IL
IL(t)
VDD
t
RG
VDD
tP
Figure 12. Unclamped Inductive Switching
Test Circuit
t, (TIME)
Figure 13. Unclamped Inductive Switching
Waveforms
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5
MMFT2N02EL
VGS
1800
Ciss
1600
Crss
VDS
Coss
TJ = 25°C
f = 1 MHz
C, CAPACITANCE (pF)
1400
1200
1000
800
Ciss
600
400
Coss
200
Crss
0
15
5
0
5
10
15
20
20
10
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 14. Capacitance Variation With Voltage
10
TJ = 25°C
VDS = 16 V
ID = 1.6 A
9
8
7
6
5
4
3
2
1
0
0
10
15
5
Qg, TOTAL GATE CHARGE (nC)
20
Figure 15. Gate Charge versus Gate–To–Source Voltage
VDD
+18V
47k
Vin
15V
1mA
5V
100k
0.1µF
2N3904
2N3904
100k
47k
SAME
DEVICETYPE
AS DUT
100
FERRITE
BEAD
DUT
Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%.
Figure 16. Gate Charge Test Circuit
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6
MMFT2N02EL
INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.15
3.8
0.079
2.0
0.091
2.3
0.248
6.3
0.091
2.3
0.079
2.0
0.059
1.5
0.059
1.5
0.059
1.5
inches
mm
SOT–223 POWER DISSIPATION
The power dissipation of the SOT–223 is a function of
the drain pad size. This can vary from the minimum pad
size for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet for the SOT–223 package, PD can be calculated as
follows:
PD =
PD =
150°C – 25°C
= 800 milliwatts
156°C/W
The 156°C/W for the SOT–223 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 800
milliwatts. There are other alternatives to achieving higher
power dissipation from the SOT–223 package. One is to
increase the area of the drain pad. By increasing the area of
the drain pad, the power dissipation can be increased.
Although one can almost double the power dissipation with
this method, one will be giving up area on the printed
circuit board which can defeat the purpose of using surface
mount technology. A graph of RθJA versus drain pad area is
shown in Figure 17.
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 800 milliwatts.
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7
MMFT2N02EL
R
JA , Thermal Resistance, Junction
to Ambient (C/W)
160
140
Board Material = 0.0625″
G-10/FR-4, 2 oz Copper
TA = 25°C
0.8 Watts
°
120
1.25 Watts*
1.5 Watts
θ
100
80
0.0
*Mounted on the DPAK footprint
0.2
0.4
0.6
A, Area (square inches)
0.8
1.0
Figure 17. Thermal Resistance versus Drain Pad
Area for the SOT–223 Package (Typical)
Another alternative would be to use a ceramic substrate
or an aluminum core board such as Thermal Clad. Using
a board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOLDER STENCIL GUIDELINES
or stainless steel with a typical thickness of 0.008 inches.
The stencil opening size for the SOT–223 package should
be the same as the pad size on the printed circuit board, i.e.,
a 1:1 registration.
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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8
MMFT2N02EL
TYPICAL SOLDER HEATING PROFILE
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 18 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 18. Typical Solder Heating Profile
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9
MMFT2N02EL
PACKAGE DIMENSIONS
SOT–223 (TO–261)
CASE 318E–04
ISSUE K
A
F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
4
S
1
2
3
B
D
L
G
J
C
0.08 (0003)
H
M
K
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10
INCHES
DIM MIN
MAX
A
0.249
0.263
B
0.130
0.145
C
0.060
0.068
D
0.024
0.035
F
0.115
0.126
G
0.087
0.094
H 0.0008 0.0040
J
0.009
0.014
K
0.060
0.078
L
0.033
0.041
M
0
10
S
0.264
0.287
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
6.30
6.70
3.30
3.70
1.50
1.75
0.60
0.89
2.90
3.20
2.20
2.40
0.020
0.100
0.24
0.35
1.50
2.00
0.85
1.05
0
10
6.70
7.30
MMFT2N02EL
Notes
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11
MMFT2N02EL
Thermal Clad is a registered trademark of the Bergquist Company.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
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Email: ONlit@hibbertco.com
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Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
001–800–4422–3781
Email: ONlit–asia@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy, UK, Ireland
For additional information, please contact your local
Sales Representative.
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MMFT2N02EL/D